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Characterizing phase-locked-loop
signal transition behaviors of
Microphonic/Phase-hits
Application Note
                   Digital communication systems often have unique carrier synchronization and syn-
    Introduction   thesizer requirements such as rapid carrier acquisition/lock, and stable operation in
                   demanding environments. The performance of these requirements is affected by not
                   only oscillator characteristics themselves but also the design of phase-locked loop cir-
                   cuits interacting with unwanted stimulus such as microphonics. This paper discusses
                   how Agilent's Signal Source Analyzer helps you to identify unwanted phase-locked loop
                   transition "phase-hits", and achieve easy, comprehensive and accurate phase-locked
                   loop characterization in both linear and nonlinear regions.




2
Characterizing PLL Linear      Starting with test parameters in characterizing phase locked loop linear and non-linear
                               behaviors; there are three different stages of test usage, component evaluation, oscil-
and Nonlinear Behaviors        lator/phase-locked-loop circuit design, and verification/test at operating conditions.

                               The PLL controls the phase of the output signal to be N times the phase of the refer-
                               ence as shown in figure 1. Similarly, the frequency of the output signal is then N times
                               the reference frequency. Like all linear feedback control systems, PLLs have dynamic
                               behavior characteristics. The linear behavior described by the transfer function
                               method is useful to analyze loop operation in the vicinity of lock. Non-linear effects
                               dominate the behavior of the PLL in unlocked conditions such as when the frequency
                               divider ratio is changed to switch frequencies over a large range.




                                Component                    Oscillator/PLL Circuit                  Verification/Test
                                 Evaluation                           Design                      at Operating Conditions

                       ` Reference Source                 ` Loop Filter (PLL Response)          ` Microphonic
                           ` Phase Noise                       ` Phase Noise
                                                               ` RF Transient                   ` Phase-hits
                       ` VCO
                           ` Phase Noise                  ` Spurs
                           ` AM Noise                     ` Harmonics
                           ` Tuning Sensitivity


                               Figure 1. Phase locked loop test parameters and challenges

                               The building blocks common to most phase locked loops are the phase detector, the loop
                               filter, the voltage controlled oscillator (VCO), and the frequency divider. Each of these
                               building blocks has both linear and non-linear attributes to its operation.




                                   Oscillator/PLL Circuit
                                            Design                                       Test Challenges


                               ` Loop Filter (PLL Response)             ` Estimate PLL response on phase noise quickly
                                    Phase Noise                         ` Fast sampling rate with sufficient frequency/
                                    RF Transient                          phase resolution are required for fast switching
                               ` Spurs                                    PLL synthesizer lockup time test
                               ` Harmonics                              ` Long jump measurement (i.e. 500 MHz)


                                 Figure 2. Test parameters and challenges in the circuit design stage




                                                                                                                             3
    Characterizing PLL Linear   PLL response in the PLL linear operating region can be characterized through phase
                                noise measurement. Once both VCO and reference phase noises are known, output
    and Nonlinear Behaviors     phase noise of the PLL can be estimated based on the designed loop filter.
    (cont'd.)
                                An RF transient characteristic known as lockup time is usually tested with the frequency
                                and phase guard band. Modern digital communication systems often require fast fre-
                                quency switching synthesizer because the available time slot of the carrier acquisition
                                is getting smaller in order to communicate multiple channels in a very short time period.
                                Typical requirement of lock up time is about 10 ms down to a single micro second order
                                level. So we need faster sampling rate measurement while we need to maintain suffi-
                                cient frequency or phase resolution.

                                Also, the frequency synthesizer needs to cover a wider frequency bandwidth due to
                                increasing bandwidth of the communication system. For example, testing of a long jump
                                frequency synthesizer as wide as 500 MHz is needed.




                                    Verification/Test
                                at Operating Conditions                                   Test Challenges


                                 Microphonic                           Difficult to capture an event that occurs randomly
                                 Phase-hits                            and unpredictably.

                                                                       Not sure to define test threshold (frequency
                                                                       resolution, time period)


                                Figure 3. Test parameters and challenges in the verification/operating test stage



                                When the designed PLL is sensitive to unwanted external physical stimulus, the system
                                may become unstable because the PLL oscillation may be modulating internally. This
                                non-linear behavior is likely to occur at various operating conditions, such as tempera-
                                ture changes, vibration, and shock.

                                Microphonic and phase-hits are known major problems and stability of the PLL needs to
                                be tested at operating conditions to address sources of unwanted behaviors.

                                The test challenges here are how to capture such events with an instrument and how
                                to analyze the signal behavior to address sources of these types of modulation, because
                                it is hard to predict when a phase-hit event occurs. Another challenge is how to define
                                the test limit to capture such an event in terms of the frequency or phase variation along
                                with duration of the event.




4
PLL Linear Behavior                      D
                                                 Loop               VCO
                                                                            V
                                 K               Filter K f     KV
Analysis
                      R                             F(s)                             OUT

                                                      



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