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HP 13255
CONTROL STORE MODULE
Manual Part No. 13255-91144
PRINTED
AUG-Ol-76
DATA TERMINAL
TECHNICAL INFORMATION
HEWLETT~PACKARD
Printed in U.S.A.
t3?'5~ 1325C;-~1150/()2
ROM (E~) Module ~ev ADR-07-i8
1 .0 INT~onurTTO~.
The RnM (~A) Module conta~ns so~ce for uo to 12v of R~M fOr storino the
o~eratinq system ilrmware.
- - ..
A summary of ~o~r~tfnq oara~eters tor the ROM (~Al Mo~ule is contained
in tahl~s 1.0 throuoh 5.0.
Tahlp. t.O Physical Parameters
-~~~--~--~~~-----------~~---~---------------~~---------~-~~~--~~-~--------------
---~-------------~---------------------------~--------.---------~----------------
Part ~ize (T:J TAl ; x
n) ~elQht
~umber Nomenclature +1-0.100 Inches (PoundS)
============= ===============:=~=~=~===~==== ----------------------- ---------
-~----~--~~------------
12.5 x 4.0 x 0.5 0.44
==:===:======:=::=:===:=======::===:===:===:::================================
Number of Backolane Slots R@aulre~:
==:=====:=:===:===========:=~======================:== =:================:=======
HP 13255
CONTROL STORE MODULE
Manual Part No. 13255-91144
PRINTED
AUG-Ol-16
----------~------------------~--~-------~~~~~~-.----.,~~~- ..--------------
NOTICE
The information contained In this document is subject to change
Without notice.
HEWLETT-PACKARD MAK~S NO WARRANTY OF ANY KIND WITH REGARD TO THIS
MATERIAL, INCLUDING, BUT NOT LIMITED TO THE IMPLI~D WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Hewlett-Packard
snall not be liable for errors contained herein Or for incidental or
consequential damages in connection with the furnishing, performance,
or use of this material.
Tnis document contains proprietary information which is protected by
copyright. All rights are reserved. No part of this document may be
Photocopied Or reproduced without the prior written consent of Hewlett-
PacKard Company.
---~-----------------~----------------~--------------- -----------_.-------------
Copyright c 1976 by HEWLETT-PACKARD COMPANy
NOTE: This document is part of the 264XX DATA TERMINAL product
series Technical Information Package (HP 13255).
13255 13255-91144/02
Control store Module Fev AUG-Ol-76
1.0 INTRODUCTION.
The Control Store MOdule c~ntains space for up to 8K Of ROM and
provides lK byte of read/write storage.
2.0 OPERATING PARAMETERS.
A summary of operating parameters for the Control store Module 1s
contained in tables 1.0 through 5.0.
Table 1.0 Physical Parameters
================================================================================
S1ze (L x W x D) Weight
Nomenclature +/-0.100 Inches (Pounds)
=============1============================== =======================1=========
02640-60144 Control Store peA 12.5 x 4.0 x 0.5 0.44
==============================================================================
Number of Backplane Slots Requ1red: 1
================================================================================
13255 13255-91144/03
Control store Module Rev AUG-Ol-76
Table 2.0 Reliability and Environmental Information
:============:===================================================================
Environmental: ( X ) HP Class B ( ) Other:
Restrictions: Type tested at product level
============.==================================================================
Failure Rate: 1.325 (percent per 1000 hours)
=============:========~=============================== ===========================
Table 3.0 Power Supply and ClOCK Requirements - Measured
(At +/-5% Unless Otherwise Specitled)
================================================================================
+5 Volt Supply +12 Volt Supply -12 Volt Supply -42 Volt ~upplY
~ 700 m.A rnA ~ 100 rnA rnA
NOT APPLICABLE NOT APPLICABLE
--~--~---~--.-----~--------~~--~~-----~ --~~~-~-~--~~-~-~--~------~-~----~~-~-~
---~-~~----~---~-----------~-------~-~ -----~--~-~---~---~-----~-------~---~~~
115 vOlts ac 220 volts ac
A A
NOT APPLICABLE NOT APPLICABLE
==============================================================================1I
Clock Frequency: 4.915 MHz +1- 0.1% I
I
t
=============:==========;=========;===~=============== ======================:====
13255 13255-91144/04
Control store Module Rev AUG-Ol-16
Table 4.0 Jumper Detlnitlons
=================-=====================================================-=========
Function
peA
Designation ----~------------.--------------~-------~-~--.-------- -------
In Out
================ ============================== ==============================
If all RAM START ADDR
Jumpers are In, then
START ADDR=O
I
I
- lK Add 0 to START ADDR Add lK to START ADDR
I 2K Add 0 to STAHT ADOR Add 2K to START AOUR
RAM I 4K Add 0 to STAHT ADDR Add 4K to START ADOR
STAHTI 8K Add 0 to START AUDR Add 8K to START ADDR
ADOR I 16K Add 0 to START ADDR Add 16K to START ADDR
I 32K Add 0 to START ADlJR Add 32K to START ADDR
t_
ROM ROM Disabled ROM Enabled
OIAG ROM Starts at 32K ROM Starts at 0
================================================================================
132~5 13255-91144/05
Control Store ~odule Bev AUG-OI-76
Table 5.0 Connector Information
================================================================================
conn~ctor Signal Signal
and Pin NO. I Name I Description
==============1================
P1, Pin 1 I +5V
-~~~~~-~---~~--~-~---~--~~-~~-~~-----~~-~-~---
--~-~~~-~-------------~-~--~---~-~--~~-------~
+5 Volt Power Supply
I
-2 I GND Ground Common Return (power and Signal)
t
-3 SYS CLK 4.915 MHz System Clock
-4 -12V -12 Volt Power Supply
-5 ADORO Negative True, Address Bit 0
-6 ADDR1 Negative True, Address Bit 1
ADL>R2 Negative True, Address Bit 2
-8 ADDR3 Negative True, Address Bit 3
-9 ADDR4 Negative True, Address Bit 4
-lO AODR5 Negative True, Address Bit 5
-1 :1 ADDR6 Negative True, Address Bit 6
-12 ADDR7 Negative True, Address Bit 7
-1:3 ADDR8 Negative True, Address Bit 8
-14 ADDR9 Negative True, Address Bit 9
-15 ADDRI0 Negative True, Address Bit 10
-16 ADDRl1 Negative True, Address Bit 11
-1'1 ADDR12 Negative True, Address Bit 12
-18 AODR13 Negative True, Address Bit 13
-19 ADOR14 Negative True, Address Bit 14
-20 AODR15 Negative True, Address Bit 15
-21 1/0 Negative True, Input OutputlMemory
GND Ground Common Return (Power and Signal)
z===z:===================================================================::=====
13255 13255-91144/06
Control Store Module Rev AUG-Ol-76
Table 5.0 Connector Information (Cont~d.)
================================-===============================================
connector Signal Signal
and Pin NO. Name Description
==============
PI, Pin A
----------------
-~-~----~--~~---
GND
-~~~~-~--~-~--~---~--~~--~-~~--~-~--~---~----~
-~----~-------~-~~---~~-----------------~-----
Ground Common Return (Power and Signal)
-8 }
)
-C ) Not Used
)
-0 )
BUSO Negative True, Data 8us Bit 0
-F BUSl Negative True, Data Bus Bit 1
-H BUS2 Negative True, Data Bus Bit 2
-J BUS3 Negative True, Data Bus Ait 3
BUS4 NeQatlve True, Data Bus Bit 4
-L 8USS Negative True, Data 6us Bit 5
RUS6 Negative true, Data B~s Bit 6
-N AUS7 Negat1ve True, uata Bus Bit 1
-p WRITE Negative true, write/Read Type Cycle
-R Not Used
-s WAIT Negative True, wait Control Line
-T PRIOR IN Bus Controller priority In
-U PRIOR OUT Bus Controller priority Out
-v }
)
-w } Not Used
}
-x }
-y REO Negative True, Request (Bus Data
currently Valid)
-z Not Used
== == == ===== = == === ==== ======= =========== =====:: =======-: =========-= = == =
= = = = =: = = == = = =
13255 13255-91144/07
Control store Module Pev AUG-01-76
3.0 fUNCTIONAL DESCRIPTION. Refer to the block diagram (figure 1),
sChematic diagram (figure 2), timing diagrams (figures 3, 4, and 5),
component location diagram (figure 6), and parts list (02640-60144)
located in the appendix.
As Shown in the block diagram, the Control Store Module contains 8K
bytes of ROM, lK byte of RAM, a RAM select coroparator, a PAM select
decoder, and associated timing and control logic.
3.1 ROM. The ROM bloCK consists of four EA 4900 Chips, each containing
2048 bytes.
3.2 ~AM. The RAM provides lK of 8-bit words ot addressable read/write
storage. It consists of eight Intel 2102 or equivalent chips, eaCh
containing 1024 bits.
3.3 RAM SELECT COMPARATOR. The RAM select comparator applies a RAM SEL
signal to the timing logic. The RAM SEL signal is determined by the
configuration Of starting address jumpers and address bits ADDR10
through ADDR15.
3.4 ~OM SELECT DECODER. The ROM select decoder decodes address bits
ADDRll through ADDRI5. ~hen a ROM address is recognized, a ROM SEL
(UJ11, Pin 6) signal is applied to the timinq logic and the appro-
priate 2K module of kOM is enabled by its SEL signal.
3.5 TIMING AND CONTROL LOGIC.
3.5.1 The timing and control logiC generates the necessary signals to perform
the read or write operation. The 93L10 counter (U32) drives the loqic
througn the states required tor the operation. The counter advances on
the negative edge of SYS CLK after the counter is enabled.
3.5.2 ROM READ. The SYS CLK, 1/0, REO, WRITE, and FOM SEL lines enable the
------
93LI0 counter (U32) and asserts the READ ADDRESS, WAIT, and ROM OUT eLK
signals. The counter advances to the states labeled in the timing dia-
gram in figure 3 on the ClOCK edges indicated bY arrows. state 2 and
the posit1ve halt of the SYS eLK drops -------
ADDRESS.
R~AD On the sixth
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