Service Manuals, User Guides, Schematic Diagrams or docs for : HP 9000_cio 27114B_CIO_Parallel_Interface_Device_Adapter_ERS_Sep89

<< Back | Home

Most service manuals and schematics are PDF files, so You will need Adobre Acrobat Reader to view : Acrobat Download Some of the files are DjVu format. Readers and resources available here : DjVu Resources
For the compressed files, most common are zip and rar. Please, extract files with Your favorite compression software ( WinZip, WinRAR ... ) before viewing. If a document has multiple parts, You should download all, before extracting.
Good luck. Repair on Your own risk. Make sure You know what You are doing.

Image preview - the first page of the document

>> Download 27114B_CIO_Parallel_Interface_Device_Adapter_ERS_Sep89 documenatation <<

Text preview - extract from the document

* * * DRAFT * * *

rh-;' HEWLETT
~~ PACKARD
Rosevil1e Networks Division

Location Code: 52-7560

Project Number: 27114B

Septem ber 1, 1989

Project Manager: John McHugh
Product Manager: Bill Wang
Development Engineer: Pery Pearson
Developrnen t Engineer: Thang Le
Diagnostic Engineer: Bill Hoope.r
Production Engineer: Ke.n Konesky
Support Engineer: Dary Wong

... HP Confidential ...

Preliminary
Revision 1. 0 11/14/88
Revision 2.001/27/89
EDITING HISTORY:

10/24/88: Outline of ERS (TL)
11/04/88: Preliminary description of registers (TL)
11/14188: Preliminary ERS (TL)
11/17/88: Correct A28/B28 pin swap mistake
Correct set/reset definition for DEND and ATTN
Add info about single-ended termination
12/08/88: General correction based on ERS review of 11/29
12/09/88: Change DEND/CEND on 27114B to PEND/HEND
Define FP data to be non-inverted
01/20/89: Drop DIAG bit, invert sense of PZERO bit in reg7
to become NZERO bit, swap header blocks +/-
01/25/89: Define FP data to be inverted (comp. with 27114A)
Clarification of EDGE and LOAD bits
03/28/89: Proof-read and corrections made for grammar and
technical accuracy.

NOTE:

This document is strictly an external reference specification
for the 2 7114B card. It only specifies what is seen and
observable at its interface points: the CIO backplane and the
parallel frontplane interface.

For more information as how it operates in a system, the readers
must confer with other documents: HP-CIO Standard Document,
the respective driver's ERS etc ...

Contrary to the expectation of some readers, this document
is not intended to be used as an ERS for the
GPIO product which consists of both a hardware (card) and a
software (driver) product. As a product, some of the card's
behaviors will be greatly influenced by how the driver is
written. That kind of information is to be covered in another
document which describes the hardware/software interaction.

It is assumed that the reader is familiar with the CIO standard
(HP-CIO STANDARD DOCUMENT, Version 2.2 - Roseville Networks
Division).

JAN 89
vii
This document is written in a format compatible with TDP's
Manu formatter, requiring no special environments. It is
currently available as a set of 12 files:

afilers afi2ers afi3ers afi42ers afi43ers afi44ers afi46ers
afi 4 7ers afi Sers afi 6ers afi 7ers afi 8ers

JAN 89
vii
~IN_T_RO_D_U_C_T_IO_N______________~I~IIII~
The 27114B is a 16 bit parallel device adapter for the CIO channel. It has a 64 level FIFO used to buffer
data between the CIO backplane and the adapter's frontplane interface. A counter is provided to allow
an exact number of handshakes to take place. The 2 7114B can interrupt the host in various situations:
end of count, end of handshake (from a peripheral) or a peripheral attention.

The 2 7114B is intended to replace the 2 7114A to remedy some of its deficiencies:

* Insufficient grounding for single-ended applications
* Vague control of frontplane handshakes due to the presence of
a FIFO
* Limited number of frontplane control and status signals
* Limited number of frontplane handshake modes
* Lack of features which allow asynchronous termination
of input/output

Some of the features which are removed from the 2 7114A are:

'* Backplane parity option
'* Pass-through frontplane parity option
'* Testhood detection capability (not available to user's program)

Besides the above changes and deletions, the following changes should also be noted for the new design of
the AFI card:

* The use of synchronous state machines throughout (no delay lines,
and no RC time delay circuits)
'* A degradation of frontplane handshake performance

As for compatibility, the 27114B should be fully compatible with the 27114A when it is used with
previously released driven (1.0 through 3.0 venions of the HP-UX/Series 800 operating system). The
27114B can be used with the old single-ended cables (but not recommended for new applications).

Since the 271 14A's on-line diagnostic is very specific to the 27114A hardware, it will not be compatible
with the new 27114B hardware. To diagnose 2 7114B cards used in systems which have older drivers and
diagnostics, the diagnostic must be updated.

As far as raw performance is concerned,the 27114B should be a slower than the 27114A. How much
impact this will have on the overall system performance remains to be seen. The slight performance
sacrifice is necessary to implement other required features in the 27114B.

1-1
'""'--T_ER_M_I_NO_L_O_G_V_D_E_F_IN_IT_I_O_NS _ _ _ _
_ I~~ml~'

2.1 INPUT /OUTPUT DEFINITION

The input direction is defined as the flow of data from the user's peripheral to the system's memory. A
read is a transaction which moves data from the 10 card to the CPU.

The output direction is defined as the flow of data from the system's memory to the user's peripheral. A
write is a transaction which moves data from the CPU to the 10 card.

2.2 WORD, BYTE AND TRANSFER

Word and byte have their usual meanings of 16 and 8 bit data units (the 32 bit word definition used by
the Spectrum program is not used here since it is always easier to say 'word' than 'half word').

Since the 2 7114B's data path is 16 bits wide, it is sometimes confusing to describe the amount of data
being tr-ansferred as N*2 bytes or N words. The rest of this document will always assume that the
27114B transfers data in the 16 bit mode. Each transfer is therefore equivalent to one 16 bit word.

2.3 LITTLE/BIG ENDIANS

This document uses the normal convention of 0 being the least significant bit in any data or address field.

2.4 LEADING/TRAILING EDGES

As a signal changes from one level to another level, it is defined as the leading edge if the change allows
the signal to be in the asserted state. When a signal changes from the asserted state to the deasserted
state,

the edge is called a trailing edge.

2.5 CIO INVERSION OF LOGIC

DATA INVERSION:

The CIO backplane is a low-true logic bus. A 1 in the program domain results in a low voltage level on
the corresponding signal and vice versa. Since the AFI card does not invert signals between itself and the
CIO bus, the same logic interpretation applies between the program domain and the hardware of the
27114B card. This must be considered when one is to work on the 27114B hardware.

2-1
Terminology definitions

This version of the ERS defines all frontplane signals such that a 0 in the user's program domain will
correspond with a low at the front plane (no logic inversion for frontplane outputs and inputs). This is
applicable to both the data and the control/status lines.

ASSER TION/DEASSERTION:

A signal is in its assertion condition when it is at the level which causes a result to happen. It is in its
deassertion condition when it is at the level which cannot cause a result. These levels can be low or high
(electrically), 0 or 1 (logically). Clarifications will be attempted in the rest of this document to qualify an
assertion condition as either low true or high true.

LOW/HIGH:

Low means the voltage is at a TTL low level, nominally below 0.8 Volts. High means the voltage is at a
TTL high level, nominally above 2.0 Volts. These will be used to indicate the conditions of various
circui ts on the 27 11 4B hard ware.

0/1:

o means a false logic in the program domain. 1 means a true logic in the program domain. When
descriptions are given in 0 and 1 or true and false, these are described in the program domain.

SET/RESET(CLEARED):

Set/reset conditions are usually used to describe the state of flipflops or register bits on the 27114B. A
set condition means the flipflop is in the asserted state and is a 1. A reset condition means the flipflop is
in the deasserted state and is a O.

CONVENTION:

* Assertion/deassertion are always qualified with low/high or
0/1 or false/true
* Hardware description uses low/high
* Logic description in the program domain uses 0/1 or false/true

2.6 GLOSSARY

Definition of terms which are unique to the 2 7114B card and its environment.

2-2
~C_ON_F_'G_U_R_A_T_IO_N______________~I~~HI,

3.1 CONFIGURATION FEATURES

To customize the 2 7114B card for any application, the user has the following choices:

* single-ended (unbalanced) or balanced differential cable
* desirable cable length (3m and 12m standard)
* the number of control lines vs other output features like
HEND and PDIR
* the number of status lines vs other input features like
PEND and ATTN
* the length of PCTL high and low time
* the hysteresis time of the PFLG signal

◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo