Service Manuals, User Guides, Schematic Diagrams or docs for : IBM Lenovo G530 N500 - COMPAL LA-4212P JIWA3 JIWA4 - REV 1.0Sec
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A B C D E
ZZZ1 ZZZ2 ZZZ3 ZZZ4 ZZZ5 ZZZ6
PCB PCB Power Switch Left LED Right LED Touch Sensor
1 DAZ@ DAZ@ DAZ@ DAZ@ DAZ@ 1
2
JIWA3/A4 2
Compal confidential Schematics Document
3
Mobile Penryn uFCPGA 3
Intel Cantiga_GM/PM+ICH9-M
Wednesday, May 14, 2008
REV:1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
Size Document Number Rev
[email protected] AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom JIWA3/A4_LA4212P 1.0
gratuito - free of charge.
A B C D
Date:
E
Sheet 1 of 53
A B C D E
ZZZ1
Compal confidential
File Name : Right LED Board Swithch & CAP SENSE LEDs Board Left LED Board
15W_PCB_LA4212P
VRAM 16*16 Mobile Penryn
1 VRAM 32*16 uFCPGA-478 CPU
1
page20,21
PCI-E X16 Clock Gen.
nVIDIA NB9M page5,6,7 SLG8SP556VTR
ICS9LPRS387AKLFT
page16,19 page22
H_A#(3..35)
FSB
H_D#(0..63) 667/800/1066MHz
HDMI Level Shifter PCI-E DDR2 -667 (1.8V)
CONN PS8101T page23 DDR2-SO-DIMM X2
page23
Intel Cantiga GMCH DDR2 -800 (1.8V) BANK 0, 1, 2, 3 page 14,15
CRT & TV OUT PCBGA 1329 Dual Channel
LVDS I/F
page25
page 8,9,10,11,12,13
2 2
LVDS
Connector page24 DMI C-Line
AMP&Audio Jack
AZALIA page24
PCI Express 6*PCI-E BUS 12*USB2.0
Mini card Slotpage32
1 Intel ICH9-M Audio Codec
mBGA-676 AMOM_CX20561 MODEM_CX20548
page30
page26,27,28,29
4*SATA serial
BCM5906 Card Reader New Card Camera Conn
10/100/LAN page33 JMB 385 LPC BUS page40
page36 page40
3 3
BlueTooth Conn
page32
RJ45 CONN EC
page34 USB conn X4
ENE KB926 page43
C version page35
Card reader(XD/SD
MMC/MS/MS-Pro Int.KBD
HD SD) page36 page37
SATA HDD
page32,36 BIOS page38
Connector page39
SUB Board Touch Pad
page37
*Right LED SATA CDROM
*Left LED Connector page39
4
*SWITCH & CAP sensor 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Block Diagram
Size Document Number Rev
[email protected] AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom JIWA3/A4_LA-4212P 1.0
gratuito - free of charge.
A B C D
Date: Monday, May 12, 2008
E
Sheet 2 of 53
A B C D E
1
Voltage Rails 1
SMBUS Control Table
Power Plane Description S1 S3 S5 THERMAL
SERIAL SENSOR
SOURCE INVERTER BATT EEPROM (CPU) SODIMM CLK CHIP MINI CARD LCD CAP BRD
VIN Adapter power supply (19V) N/A N/A N/A
B+ AC or battery power rail for power circuit. N/A N/A N/A
+CPU_CORE Core voltage for CPU ON OFF OFF
SMB_EC_CK1
SMB_EC_DA1
KB926 X V V X X X X X X
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF
+1.05VS 1.05V switched power rail ON OFF OFF
SMB_EC_CK2
SMB_EC_DA2
KB926 X X X V X X X X V
SMB_CK_CLK1
+1.5VS
+1.8V
1.5V switched power rail
1.8V power rail for DDR
ON
ON
OFF
ON
OFF
OFF
SMB_CK_DAT1 ICH9 X X X X V V V X X
+1.8VS 1.8V switched power rail ON OFF OFF LCD_CLK
+2.5VS 2.5V switched power rail ON OFF OFF
LCD_DAT Cantiga
X X X X X X X V X
+3VALW 3.3V always on power rail ON ON ON*
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON*
2 2
+5VS 5V switched power rail ON OFF OFF
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
3 3
PM@
GM@
X76@
CARD@
WLAN@
HDMI@
HDMI_PM@
HDMI_GM@
BT@
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Notes List
Size Document Number Rev
[email protected] AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B JIWA3/A4_LA4212P 1.0
gratuito - free of charge.
A B C D
Date: Monday, May 12, 2008
E
Sheet 3 of 53
A B C D E
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+VGA_CORE Core voltage for GPU ON OFF OFF
+1.1VS 1.1V switched power rail ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.8V 1.8V power rail for DDR ON ON OFF
+1.8VS 1.8V switched power rail ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON*
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON*
+5VS 5V switched power rail ON OFF OFF POWER SQUENCE
+VSB VSB always on power rail ON ON ON*
The ramp time for any rail must be more than 40us
+RTCVCC RTC power ON ON ON
EDP at Tj = 97C*
Power Supply Rail NB9M-GS NB9M-GE
(V) GDDR3 DDR2 GDDR3 DDR2 (+3VS) VDD33
NVVDD Variable 12.68A 11.57A 10.52A 9.59A
2
FB_DLLAVDD 1.1 25mA 2
FB_PLLAVDD 1.1 10mA PEX_VDD can ramp up any time
IFPC_IOVDD 1.1 385mA
IFPD_IOVDD 1.1 385mA (1.1VS) PEX_VDD
IFPE_IOVDD 1.1 385mA
tNVVDD>=0
IFPF_IOVDD 1.1 385mA
PEX_IOVDD/Q 1.1 1400mA
PEX_PLLVDD 1.1 110mA (+VGA_CORE) NVVDD
PLLVDD 1.1 65mA tNV-FB
SP_PLLVDD 1.1 25mA
tFBVDDQ>=0
VID_PLLVDD 1.1 50mA
TOTAL 1.1 3.225A
(1.8VS) FBVDDQ
FBVDD/Q 1.8 3080mA 1720mA 3010mA 1680mA
IFPA_IOVDD 1.8 50mA
IFPB_IOVDD 1.8 50mA
IFPAB_PLLVDD 1.8 100mA
3 3
IFPCD_PLLVDD 1.8 160mA
IFPEF_PLLVDD 1.8 160mA
TOTAL 1.8 3.6A 2.24A 3.53A 2.2A
DACA_VDD 3.3 130mA
DACB_VDD 3.3 255mA
DACC_VDD 3.3 130mA
MIOA_VDDQ 3.3 10mA
MIOB_VDDQ 3.3 10mA
VDD33 3.3 110mA
TOTAL 3.3 0.645A
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
Size Document Number Rev
[email protected] AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B JIWA3/A4_LA4212P 1.0
gratuito - free of charge.
A B C D
Date: Monday, May 12, 2008
E
Sheet 4 of 53
5 4 3 2 1
XDP Reserve +3VS
XDP_DBRESET# 1 2 @ 1K_0402_5%
R43
+VCCP
XDP_TDI R11 1 2 54.9_0402_1%
D XDP_TMS R14 1 2 54.9_0402_1% D
ME@ +VCCP XDP_TDO R12 1 @ 2 54.9_0402_1%
<8> H_A#[3..16]
JCPUA
H_A#3 J4 H1 H_ADS# R13 1 2 54.9_0402_1%
A[3]# ADS# H_ADS# <8>
ADDR GROUP_0
ADDR GROUP_0
H_A#4 L5 E2 H_BNR#
A[4]# BNR# H_BNR# <8> reserved by XDP_BPM#5
H_A#5 L4 G5 H_BPRI# @
A[5]# BPRI# H_BPRI# <8>
1
H_A#6 K5 R83
H_A#7 A[6]# H_DEFER# 56_0402_5%
M3 A[7]# DEFER# H5 H_DEFER# <8>
H_A#8 N2 F21 H_DRDY# XDP_TRST# R16 1 2 54.9_0402_1%
A[8]# DRDY# H_DRDY# <8>
H_A#9 J1 E1 H_DBSY#
A[9]# DBSY# H_DBSY# <8>
H_A#10 N3 XDP_TCK R15 1 2 54.9_0402_1%
2
H_A#11 A[10]# H_BR0#
P5 A[11]# BR0# F1 H_BR0# <8>
H_A#12 P2 A[12]#
CONTROL
H_A#13 L2 D20 H_IERR#
H_A#14 A[13]# IERR# H_INIT#
P4 A[14]# INIT# B3 H_INIT# <27>
H_A#15 P1
H_A#16 A[15]# H_LOCK#
R1 A[16]# LOCK# H4 H_LOCK# <8>
H_ADSTB#0 M1
<8> H_ADSTB#0 ADSTB[0]#
C1 H_RESET#
RESET# H_RESET# <8>
H_REQ#0 K3 F3 H_RS#0
<8> H_REQ#0 REQ[0]# RS[0]# H_RS#0 <8> +3VS
H_REQ#1 H2 F4 H_RS#1
<8> H_REQ#1 REQ[1]# RS[1]# H_RS#1 <8> +3VS
H_REQ#2 K2 G3 H_RS#2
<8> H_REQ#2 REQ[2]# RS[2]# H_RS#2 <8>
H_REQ#3 J3 G2 H_TRDY#
<8> H_REQ#3 REQ[3]# TRDY# H_TRDY# <8>
2
H_REQ#4 L1
<8> H_REQ#4 REQ[4]# H_HIT# R95
0.1U_0402_16V4Z
<8> H_A#[17..35] HIT# G6 H_HIT# <8> 1
H_A#17 Y2 E4 H_HITM# 10K_0402_5%
A[17]# HITM# H_HITM# <8> C89
H_A#18 U5
H_A#19 A[18]# XDP_BPM#0
R3 AD4
1
A[19]# BPM[0]# 2
ADDR GROUP_1
C H_A#20 W6 AD3 XDP_BPM#1 C
H_A#21 A[20]# BPM[1]# XDP_BPM#2 U5
U4 A[21]# BPM[2]# AD1
H_A#22 Y5 AC4 XDP_BPM#3 1 8 EC_SMB_CK2 EC_SMB_CK2 <16,35,41>
H_A#23 A[22]# BPM[3]# XDP_BPM#4 VDD SCLK
XDP/ITP SIGNALS
U1 A[23]# PRDY# AC2
H_A#24 R4 AC1 XDP_BPM#5 XDP_BPM#5 reserve a via for debuging H_THERMDA 2 7 EC_SMB_DA2
A[24]# PREQ# D+ SDATA EC_SMB_DA2 <16,35,41>
H_A#25 T5 AC5 XDP_TCK C95
H_A#26 A[25]# TCK XDP_TDI H_THERMDC
T3 A[26]# TDI AA6 1 2 3 D- ALERT/THERM2 6
H_A#27 W2 AB3 XDP_TDO 2200P_0402_50V7K
H_A#28 A[27]# TDO XDP_TMS THERM#
W5 A[28]# TMS AB5 4 THERM GND 5
H_A#29 Y4 AB6 XDP_TRST#
H_A#30 A[29]# TRST# XDP_DBRESET# R94
U2 A[30]# DBR# C20 XDP_DBRESET# <28>
H_A#31 V4 1 2 S IC EMC1402-1-ACZL-TR MSOP 8P
A[31]# +3VS
H_A#32 W3 2 1 10K_0402_5%
H_A#33 A[32]# R84 68_0402_5% +VCCP
AA4 A[33]# THERMAL Address:100_1100
H_A#34 AB2 H_PROCHOT#
A[34]# H_PROCHOT#
H_A#35 AA3 D21
H_ADSTB#1 A[35]# PROCHOT# H_THERMDA
<8> H_ADSTB#1 V1 ADSTB[1]# THERMDA A24
B25 H_THERMDC
H_A20M# THERMDC
<27> H_A20M# A6 A20M#
ICH
ICH
H_FERR# A5 C7 H_THERMTRIP#
<27> H_FERR# FERR# THERMTRIP# H_THERMTRIP# <8,27>
H_IGNNE# C4
<27> H_IGNNE# IGNNE#
H_STPCLK# D5
<27> H_STPCLK# STPCLK#
H_INTR C6 H CLK
<27> H_INTR
<27> H_NMI
H_NMI
H_SMI#
B4
A3
LINT0
LINT1 BCLK[0] A22
A21
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_CPU_BCLK <22> FAN1 Conn
<27> H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# <22>
M4 +5VS +5VS
RSVD[01] C594 10U_0805_10V4Z
B
N5 RSVD[02] H_THERMDA, H_THERMDC routing together, B
T2 RSVD[03] 1 2
1
V3 Trace width / Spacing = 10 / 10 mil
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