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     inter
     iAPX 432
     Interface Processor
     Architecture Reference Manual




171863-001
                               INTEL

                    iAPX 432 INTERFACE   P~OR




                  Manual Orner Number 171863-001



                      Release 1.1 Oamponents




               Cb~right   (C) 1981, Intel Corporation
Intel Corporation, 3065 Bowers Avenue, Santa Clara, California 95051
Additional oopies of this manual or other Intel literature may be
obtained from:

     Literature Department
     Intel Corporation
     3065 BCMers Avenue
     Santa Clara, CA 95051


The information in this document is subject to change without notice.

Intel Corporation makes no warranty of any kind with regard to this
material, including, but not limited to, the inplied warranties of
merchantability and fitness for a particular p..1rpose.         Intel
Corporation assumes no responsibility for any errors that may appear
in this document. Intel Corporation makes 00 camti trnent to update
oor to keep current the information oontained in this document.


Intel Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in an Intel product. No
other circuit patent licenses are ~lied.


Intel software products are oopyr ighted by and shall remain the
property of Intel Corporation. Use, duplication, or disclosure is
subject to restrictions stated in Intel's software license, or as
defined in ASPR 7-104.9 (a) (9).


No part of this document may be copied or reproduced in any form or
by any means without the prior written consent of Intel Corporation.


The following are trademarks of Intel Corporation and its affiliates
am may be used only to identify Intel products:

     BXP                Intelevision                    Micrornap
     CREDIT             IntellecR                       MultibusR
     iR                 iRMX                            MultiIOOdule
     ICE                iSBC                            Plug-A-Bubble
     iCS                iSBX                            PROMPT
     ~                  Library Manager                 Promware
     INSITE             M:SR                            ~/80
     IntelR             Megachassis                     System 2000 R
     intelR             Micromainframe                  UPI
                                                        uSoope

and the combination of lCE,- iCS,   i~,   iSBC, iSBX,   ~,   or RMX and a
numerical suffix.




ii
                                                        PREFACE




Understanding any complex comp.lting system, such as the Intel iAPX
432, requires the assimilation of a great deal of technical
information. Before reading this manual on the architecture of the
432 Interface Processor, the reader should have conmand of the
general 432 concepts. Intel offers three documents which provide
these prerequisites.

   o    The INTEL 432 System Summary, Order Number 171867, provides
        the broad picture of the 432. It should be read as a first
        introduction to the 432 system.

   o    The Introduction to the iAPX 432 Architecture, Order Number
        171821, restricts discussion to general architecture
        features which distinguish the 432.

   o    The iAPX 432 General Data Processor Archi tecure Reference
        Manual,   Order   Number   171860-001,  provides   detailed
        information on one type of 432 processor, a General Data
        Processor (GOP). Its glossary is a concise surrmary of the
        rrost important terminology which is required when reading
        the Interface Processor manual.

This manual describes another 432 processor, the Interface Processor
(IP), similar in many respects to a GOP and different in others.
Rather than duplicate all of the general 432 information oontained
in the companion documents, this manual relies 00 the above
references for descr iptions of features of 432 archi tecture which
are common among processors. Unique features am functions of the
IP are presented and oontrasted with those of the GOP when
appropriate.

Chapters 1 through 6 of this manual are oomposedof descriptions of
the Interface Processor, allowing the reader to understand the
cx:x>peration between an IP and Peripheral Subsystems in forming a
logical I/O processor for a 432 system. Detailed representations
for the objects, descriptions of windCMs and functions, faults,
interrupts, am initialization may be foum in the apperrlices.




                                                                  iii
                                                      TABLE OF CCNl'ENI'S




TITLE                                                                          PAGE
1.   KE'Y'   crncEP'l'S ...

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