Service Manuals, User Guides, Schematic Diagrams or docs for : Keithley Appnotes 2962_Semiconductor_Manufacturing
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A GREAT ER M EA SU R E O F C O N F I D E N C E for NBTI identifies "NBTI recovery during
interim measurements" as the concern that
motivates reliability researchers to continue
to refine test techniques. Experimental data
reveals that the time slope of measured
degradation is strongly dependent on meas-
urement delay and measurement speed.
Several measurement techniques have
been developed to minimize measurement
delay and increase measurement speed while
monitoring process-induced BTI shifts.
Each of these techniques has benefits and
drawbacks. Here we examine some of these
techniques including on-the-fly measure-
On-The-Fly
ments and discuss the instrument require-
ments related to effective implementations
of BTI application.
Threshold Voltage On-the-fly (OTF) techniques
BTI characterization is becoming a
Measurement for BTI critical test in semiconductor design and
fabrication. Denais et al. have proposed a
Characterization
method to minimize recovery during interim
measurements by using an indirect measure-
ment that could be correlated to VTH shifts.
The interim measurement was designed to
reduce the "off-stress" time by using only
three measurements, as shown in Figure 1.
Paul Meyer, Keithley Instruments, Inc. Almost any parametric measurement system
can support this technique. However, most
GPIB-controlled instruments lack flexibility
Advances in traditional CMOS scaling the transistor, which leaves BTI as the limit- and are limited by GPIB communication
techniques are reaching their limits, bring- ing factor. time and the internal speed of the instrument.
ing up the need for new materials and novel The need to monitor and control bias tem- As a result, the device can remain unstressed
device designs. Along with these new materi- perature instability--both negative (NBTI) for roughly 100ms during the measurement.
als and designs comes a new emphasis on and positive (PBTI)--in both scaled CMOS These limitations can obscure visibility into
latent failure mechanisms and the need for and precision analog CMOS technologies degradation and recovery within the 100ms
more reliability testing. Failure mechanisms is growing. The current JEDEC standard time limit.
such as bias temperature instability (N-BTI
and P-BTI) require high speed source and
measure capability to resolve fast recovery VD at small bias
affects. An examination of measurement to enable ID
techniques, including on-the-fly measure- measurement
with minimal field
ments, will aid in implementing effective
measurement solutions with the proper VD
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