Service Manuals, User Guides, Schematic Diagrams or docs for : LENOVO Laptop IdeaPad B460 V460
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5 4 3 2 1
USB BD
Thermal
Sensor
Clock GEN LA46 UMA Block Diagram PCB LAYER
CK505
I/O BD EMC2103 L1: Top
11 3 LA46-UMA-1_0104 L2: VCC
L3: Signal
D CRT BD Project Code: 91.4GV01.001 L4: Signal D
UNBUFFERED Channel A
DDR3 SODIMM PCB(Raw Card): 09922-1 L5: GND
DDR3 800/1066 Intel CPU L6: Bottom
Socket1 Auburndale
Power BD 12
(Dual Core)
204-PIN DDR3 SODIMM
Finger Printer BD UNBUFFERED Channel B DDR3 800/1066MHz CPU DC/DC
DDR3 SODIMM DDR3 800/1066 ISL62882 38,39
Socket2 4,5,6,7,8,9,10
AV BD INPUTS OUTPUTS
13
DCBATOUT VCC_CORE
FDI DMI x4
BT BD SYSTEM DC/DC
TPS51123 40
INPUTS OUTPUTS
Intel 5V_AUX_S5
PCH HM55 DCBATOUT
3D3V_AUX_S5
5V_S5
3D3V_S5
USB 2.0 (12 ports) LVDS
14'' WUXGA
C Mic in (WSXGA) LCD 24 C
HD AUDIO CODEC HDA Link Serial ATA (4 ports) SYSTEM DC/DC
PCI Express (8 ports) RT8209E 41
ALC269Q-VB-GR RGB CRT CONN
AC97 2.3/Azalia Interface 25 INPUTS OUTPUTS
ACPI 2.0 DCBATOUT 1D5V_S3
Headphone out 27
LPC I/F
PCI Express 1 GLAN Transformer RJ45 SYSTEM DC/DC
PCI Rev 2.3
AR8131 29 RT8209E 41
INT. RTC
INPUTS OUTPUTS
SATA CONN SATA Port 0 DCBATOUT 1D05V_S0
SATA HDD
28
USB 2.0 CH3
14,15,16,17,18,19,20,21,22
Mini PCI-E SYSTEM DC/DC
31 42
SATA ODD SATA CONN SATA Port 4
PCI Express 2
WLAN Card RT8209E
28
INPUTS OUTPUTS
DCBATOUT 1D05V_VTT
USB 2.0 CH5
5-in-1 MediaCard Reader USB 2.0 CH4 Mini PCI-E SIM Slot LDO
Slot Realtek/5159 31 43
PCI Express 3
WWAN Card 31 RT9025
INPUTS OUTPUTS
3D3V_S5 1D8V_S0
B Bluetooth
32
CH9 B
USB 2.0 CH12
EHCI#1
Express Card
LDO
I/O BD RT9026 43
Camera CH15
24 PCI Express 4 31 INPUTS OUTPUTS
0D75_S0
1D5V_S3 DDR_VREF_S3
Finger Printer CH10
35
SYSTEM DC/DC
SPI
LPC Bus / 33MHz
ISL62881 44
USB 2.0
USB 2.0 CH1 INPUTS OUTPUTS
USB BD 32
SPI FLASH DCBATOUT VCC_GFXCORE
KBC LPC Debug
4MB
CH2
Nuvoton NPCE781E
USB 2.0 35
32 33 33 CHARGER
BQ24745 46
USB 2.0 CH8 INPUTS OUTPUTS
32
Multi-touch Int. KB G-Sensor SPI Flash DCBATOUT BT+
Touchpad 128Kb
33 35 35
A A
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Title
Block Diagram
Size Document Number Rev
1
LA46-UMA
Date: Monday, January 18, 2010 Sheet 1 of 48
5 4 3 2 1
5 4 3 2 1
Processor Strapping Sequence AC
Pin Name Strap Description Configuration (Default value for each bit is Default AD+
PLANAR_ID[1..0]
1 unless specified otherwise) Value KBC GPIn 31 23
3D3V_AUX_S5
CFG[4] Embedded 1: Disabled - No Physical Display Port attached to 1 Planar ID Version Planar PCB Version
DisplayPort Embedded DisplayPort. 5V_AUX_S5 PLANAR_IDn 1 0
Presence 0: Enabled - An external Display Port device is
connected to the Embedded Display Port. S5_ENABLE (KBC) 0 0 LA46_UMA- SA SA
CFG[3] PCI-Express Static 1: Normal Operation. 1
Lane Reversal 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ... 5V_S5 0 1 LA46_UMA- SB SB
D CFG[0] PCI-Express 1: Single PCI-Express Graphics 1
3D3V_S5 >10ms
1 0 LA46_UMA- SC SC
D
Configuration 0: Bifurcation enabled
RSMRST#_KBC
Select 1 1 LA46_UMA- 1 -1
CFG[7] Reserved - Clarksfield (only for early samples pre-ES1) - 0 can power after power switch press
Temporarily used Connect to GND with 3.01K Ohm/5% resistor LAN_PWR_ON
for early Note: Only temporary for early CFD samples
Clarksfield (rPGA/BGA) [For details please refer to the WW33
samples. MoW and sighting report]. 3D3V_LAN_S5
For a common motherboard design (for AUB and CFD),
the pull-down resistor should be used. Does not 7,36,38 VCC_CORE VCC_CORE
impact AUB functionality. KBC_PWRBTN#
11,20,21,24,25,26,27,28,35,36,43,48 5V_S0 5V_S0
3,5,11,12,13,14,15,16,17,18,19,20,21,24,25,26,27,31,32,33,34,35,36,37,39,40,42,43 3D3V_S0 3D3V_S0
PM_PWRBTN#
5,8,12,13,36,40,42 1D5V_S3 1D5V_S3
3,14,15,16,20,21,36,40 1D05V_S0 1D05V_S0
PM_SLP_S4#
5,7,8,19,20,21,36,37,41 1D05V_VTT 1D05V_VTT
PCH Strapping 1D5V_S3
DDR3_VREF_S3
8,20,36,42 1D8V_S0
12,13,42 DDR_VREF_S3
1D8V_S0
DDR_VREF_S3
8,36,43 VCC_GFXCORE VCC_GFXCORE
Name Schematics Notes PM_SLP_S3#
SPKR Reboot option at power-up
Default Mode: Internal weak Pull-down.
5V_S0
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-k
- 10-k weak pull-up resistor. 3D3V_S0
1D8V_S0
INIT3_3V# Weak internal pull-down. Do not pull high. 1D5V_S0
C GNT3#/
GPIO55
Default Mode: Internal pull-up.
Low (0) = Top Block Swap Mode (Connect to ground with 4.7-k weak
1D05V_S0
0D75V_S0 C
pull-down resistor). ALL_PWRGD
INTVRMEN High (1) = Integrated VRM is enabled
Low (0) = Integrated VRM is disabled
1D05V_VTT
GNT0#, Default (SPI): Left both GNT0# and GNT1# floating. No pull up
GNT1# required.
Boot from PCI: Connect GNT1# to ground with 1-k pull-down VTT_PWRGD
resistor. Leave GNT0# Floating. (H_VTTPWRGD -->CPU, KBC)
Boot from LPC: Connect both GNT0# and GNT1# to ground with 1-k
pull-down resistor.
GFX_VR_EN
GNT2#/ Default - Internal pull-up.
GPIO53 Low (0)= Configures DMI for ESI compatible operation (for servers
only. Not for mobile/desktops). VCC_GFXCORE
GPIO33 Default: Do not pull low.
Disable ME in Manufacturing Mode: Connect to ground with 1-k
DIS
pull-down resistor.
DGPU_PWR_EN#
SPI_MOSI Enable iTPM: Connect to Vcc3_3 with 8.2-k weak pull-up resistor.
Disable iTPM: Left floating, no pull-down required.
NV_ALE Enable Danbury: Connect to Vcc3_3 with 8.2-k weak pull-up 3D3V_S0_NV
resistor.
Disable Danbury: Connect to ground with 4.7-k weak pull-down
resistor. VGA_CORE_PWR
NC_CLE Weak internal pull-up. Do not pull low.
HAD_DOCK_EN# Low (0): Flash Descriptor Security will be overridden. DGPU_PWROK
/GPIO[33] High (1) : Flash Descriptor Security will be in effect.
B HDA_SDO Weak internal pull-down. Do not pull high.
1D8V_S0_NV B
HDA_SYNC Weak internal pull-down. Do not pull high. FBVDD
GPIO15 Weak internal pull-down. Do not pull high. 1D05V_S0_NV
GPIO8 Weak internal pull-up. Do not pull low.
GPIO27 Default = Do not connect (floating)
High(1) = Enables the internal VccVRM to have a clean supply for >99ms
analog rails. No need to use on-board filter circuit. S0_PWR_GOOD
Low (0) = Disables the VccVRM. Need to use on-board filter (IMVP_VR_EN)
circuits for analog rails.
VCC_CORE
VR_CLKEN#
CORE_PWRGD
(SYS_PWROK, PCH_PWROK)
Platform controlled
Sillicon controlled
PM_DRAM_PWRGD
H_PWRGD
PLT_RST#
A A
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Title
Reference
Size Document Number Rev
A2 1
LA46-UMA
Date: Monday, January 18, 2010 Sheet 2 of 48
5 4 3 2 1
5 4 3 2 1
FOR CO-LAY SLG8LV595
1D5V_S0 1D5V_S0_CK505
1 2
D R159
D
0R3J-0-U-GP
-1 1229
1
1D05V_S0 1D05V_CK505
-1 1229 DY R154
3D3V_S0 3D3V_CK505 1D5V_S0_CK505 0R3J-0-U-GP
3D3V_CK505 1D05V_CK505 1 R165 2
1 R134 2 0R0603-PAD-1-GP
2
1
1
1
1
0R0603-PAD-1-GP C199 C198 C174 C191
1
1
1
1
1
C140 C124 C137 C159 C123
1
1
SC47P50V2JN-3GP
SC47P50V2JN-3GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SCD1U16V2ZY-2GP
C190 C125
2
2
2
2
SC10U10V5ZY-1GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SC47P50V2JN-3GP
2
2
2
2
2
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
2
24
17
29
15
18
1
5
U1
VDD_CPU
VDD_SRC
VDD_REF
VDD_DOT
VDD_27
VDD_SRC_IO
VDD_CPU_IO
15 DREFCLK# 4 6 TP_27M 1 TP18
DOT_96# 27MHZ TP_27MSS TP19 3D3V_CK505
15 DREFCLK 3 7 1
DOT_96 27MHZ_SS
R150
C 15 CLKIN_DMI#
15 CLKIN_DMI
14
13
SRC_2#
16 CPU_STOP# 2 1
C
SRC_2 CPU_STOP# CK_PW RGD TP31 10KR2J-3-GP
25 1
CKPWRGD/PD# REF_0/CPU_SEL R138 1
15 CLK_PCIE_SATA# 11 30 2 33R2J-2-GP CLK_ICH14 15
SRC_1/SATA# REF_0/CPU_SEL
15 CLK_PCIE_SATA 10 SRC_1/SATA
1
15 CLK_CPU_BCLK# 22 28 GEN_XTAL_IN
CPU_0# XTAL_IN GEN_XTAL_OUT C132
15 CLK_CPU_BCLK ◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo