Service Manuals, User Guides, Schematic Diagrams or docs for : LENOVO Laptop LA46-Dis
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5 4 3 2 1
LA46 Switchable Graphics System Schematics Project Code: 91.4GV01.001 USB BD PCB LAYER
PCB(Raw Card): 09911-1 L1: Top
L2: GND
I/O BD L3: Signal
Thermal Clock GEN VRAM DDR3 X4
Sensor CK505 512MB / 1GB L4: Signal
EMC2103 PortA 57,58 L5: VCC
11 3 CRT BD L6: Signal
D L7: GND D
L8: Signal
UNBUFFERED Power BD
Channel A
DDR3 SODIMM
DDR3 800/1066 Intel CPU NVIDIA
Socket1 Auburndale CPU DC/DC
12 Finger Printer BD 38,39
(Dual Core) N11M-GE ISL62882
204-PIN DDR3 SODIMM PCIe 16X Gen2 HDMI HDMI CONN 26 INPUTS OUTPUTS
UNBUFFERED Channel B DDR3 800/1066MHz HDMI BD DCBATOUT VCC_CORE
HDMI BD
DDR3 SODIMM DDR3 800/1066
Socket2 4,5,6,7,8,9,10 54,55,56,57,58,59 SYSTEM DC/DC
13 TPS51123 40
BT BD
INPUTS OUTPUTS
FDI DMI x4 RGB LVDS 5V_AUX_S5
3D3V_AUX_S5
Mic in AV BD DCBATOUT 5V_S5
3D3V_S5
14'' WUXGA
HD AUDIO CODEC HDA Link LVDS LVDS SYSTEM DC/DC
Intel (WSXGA) LCD 24 41
PCH HM55 MUX RT8209E
ALC269Q-VB-GR
INPUTS OUTPUTS
C 27
USB 2.0 (12 ports)
RGB
23,24,25
RGB CRT CONN 25 DCBATOUT 1D5V_S3 C
Serial ATA (4 ports) CRT BD
Headphone out PCI Express (8 ports) SYSTEM DC/DC
RT8209E 41
AC97 2.3/Azalia Interface
INPUTS OUTPUTS
ACPI 2.0 DCBATOUT 1D05V_S0
LPC I/F
GLAN
PCI Express 8 AR8131 Transformer RJ45
PCI Rev 2.3 30 SYSTEM DC/DC
29 42
INT. RTC 30 RT8209E
INPUTS OUTPUTS
SATA HDD SATA CONN SATA Port 0
28 DCBATOUT 1D05V_VTT
14,15,16,17,18,19,20,21,22 USB 2.0 CH2 Mini PCI-E
WLAN Card LDO
SATA ODD SATA CONN SATA Port 1
43
28
PCI Express 1
RT9025
INPUTS OUTPUTS
3D3V_S5 1D8V_S0
I/O BD
USB 2.0 CH4 Mini PCI-E
5-in-1 MediaCard Reader USB 2.0 port? LDO
WWAN Card SIM Slot 43
Slot Realtek/5138 RT9026
PCI Express 3 INPUTS OUTPUTS
0D75_S0
B Bluetooth CH3
1D5V_S3 DDR_VREF_S3
B
32 USB 2.0 CH6
Express Card SYSTEM DC/DC
EHCI#1
ISL62881 44
Camera CH5 PCI Express 4 I/O BD INPUTS OUTPUTS
24 31
DCBATOUT VCC_GFXCORE
Finger Printer CH7 SYSTEM DC/DC
38 45
ISL62872
SPI
LPC Bus / 33MHz
INPUTS OUTPUTS
USB 2.0
USB 2.0 CH7
35 DCBATOUT VGA_CORE_S0
USB BD
SPI FLASH KBC LPC Debug
4MB
Nuvoton NPCE781E Board Conn CHARGER
CH8 38 BQ24745 46
USB 2.0
35 36 36
INPUTS OUTPUTS
CH0 DCBATOUT BT+
USB 2.0
35
Multi-touch Int. KB G-Sensor SPI Flash
Touchpad 128Kb
38 36 38 38
A A
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Title
01_Block Diagram
Size Document Number Rev
Custom -1
LA46 MB DIS
Date: Wednesday, January 27, 2010 Sheet 1 of 58
5 4 3 2 1
5 4 3 2 1
Processor Strapping Sequence AC
Pin Name Strap Description Configuration (Default value for each bit is Default
AD+
1 unless specified otherwise) Value
CFG[4] Embedded 1: Disabled - No Physical Display Port attached to 1 3D3V_AUX_S5
DisplayPort Embedded DisplayPort.
5V_AUX_S5
Presence 0: Enabled - An external Display Port device is
connected to the Embedded Display Port.
S5_ENABLE (KBC)
CFG[3] PCI-Express Static 1: Normal Operation. 1
Lane Reversal 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ...
5V_S5
D CFG[0] PCI-Express
Configuration
1: Single PCI-Express Graphics
0: Bifurcation enabled
1 3D3V_S5 >10ms D
Select RSMRST#_KBC
CFG[7] Reserved - Clarksfield (only for early samples pre-ES1) - 0
Temporarily used Connect to GND with 3.01K Ohm/5% resistor can power after power switch press
LAN_PWR_ON
for early Note: Only temporary for early CFD samples
Clarksfield (rPGA/BGA) [For details please refer to the WW33
samples. MoW and sighting report]. 3D3V_LAN_S5
For a common motherboard design (for AUB and CFD),
the pull-down resistor should be used. Does not
impact AUB functionality. KBC_PWRBTN#
PM_PWRBTN#
PCH Strapping PM_SLP_S4#
Name Schematics Notes
1D5V_S3
SPKR Reboot option at power-up DDR3_VREF_S3
Default Mode: Internal weak Pull-down.
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-k
- 10-k weak pull-up resistor. PM_SLP_S3#
INIT3_3V# Weak internal pull-down. Do not pull high.
5V_S0
GNT3#/ Default Mode: Internal pull-up. 3D3V_S0
GPIO55 Low (0) = Top Block Swap Mode (Connect to ground with 4.7-k weak 1D8V_S0 PLANAR_ID[1..0]
pull-down resistor). 1D5V_S0
1D05V_S0 KBC GPIn 31 23
C INTVRMEN High (1) = Integrated VRM is enabled
Low (0) = Integrated VRM is disabled
0D75V_S0
PLANAR_IDn 1 0
Planar ID Version Planar PCB Version C
GNT0#, Default (SPI): Left both GNT0# and GNT1# floating. No pull up ALL_PWRGD
GNT1# required.
0 0 LA46 - SA SA
Boot from PCI: Connect GNT1# to ground with 1-k pull-down
resistor. Leave GNT0# Floating. 1D05V_VTT
0 1 LA46 - SB SB
Boot from LPC: Connect both GNT0# and GNT1# to ground with 1-k
pull-down resistor.
VTT_PWRGD 1 0 LA46 - SB SC
GNT2#/ Default - Internal pull-up. (H_VTTPWRGD -->CPU, KBC)
GPIO53 Low (0)= Configures DMI for ESI compatible operation (for servers
only. Not for mobile/desktops). 1 1 -1
GFX_VR_EN
GPIO33 Default: Do not pull low.
Disable ME in Manufacturing Mode: Connect to ground with 1-k
pull-down resistor. VCC_GFXCORE
SPI_MOSI Enable iTPM: Connect to Vcc3_3 with 8.2-k weak pull-up resistor.
Disable iTPM: Left floating, no pull-down required. DIS: Before 1D05V_VTT 7,36,39 VCC_CORE VCC_CORE
NV_ALE Enable Danbury: Connect to Vcc3_3 with 8.2-k weak pull-up
resistor. DGPU_PWR_EN# 11,20,21,23,24,25,26,27,28,35,36,44,45,48,49 5V_S0 5V_S0
Disable Danbury: Connect to ground with 4.7-k weak pull-down 3,5,11,12,13,14,15,16,17,18,19,20,21,23,24,25,26,27,31,32,33,34,35,36,38,41,43,44,50 3D3V_S0 3D3V_S0
resistor.
3D3V_S0_NV 5,8,12,13,36,41,43,50 1D5V_S3 1D5V_S3
NC_CLE Weak internal pull-up. Do not pull low.
3,14,15,16,20,21,41,50 1D05V_S0 1D05V_S0
HAD_DOCK_EN# Low (0): Flash Descriptor Security will be overridden.
/GPIO[33] High (1) : Flash Descriptor Security will be in effect. VGA_CORE_PWR 5,7,8,19,20,21,36,38,42 1D05V_VTT 1D05V_VTT
HDA_SDO Weak internal pull-down. Do not pull high. 8,20,23,36,43 1D8V_S0 1D8V_S0
HDA_SYNC Weak internal pull-down. Do not pull high. DGPU_PWROK 12,13,43 DDR_VREF_S3 DDR_VREF_S3
GPIO15 Weak internal pull-down. Do not pull high. 8,36,44 VCC_GFXCORE VCC_GFXCORE
B GPIO8 Weak internal pull-up. Do not pull low. 1D8V_S0_NV
FBVDD
B
GPIO27 Default = Do not connect (floating) 45,50,51,53,54,55 3D3V_S0_NV 3D3V_S0_NV
1D05V_S0_NV
High(1) = Enables the internal VccVRM to have a clean supply for
analog rails. No need to use on-board filter circuit. 45,50,51 VGA_CORE_S0 VGA_CORE_S0
Low (0) = Disables the VccVRM. Need to use on-board filter 50,54 1D8V_S0_NV 1D8V_S0_NV
circuits for analog rails.
>99ms 50,52,57,58 FBVDD FBVDD
S0_PWR_GOOD
(IMVP_VR_EN) 50,51,52,54,55 1D05V_S0_NV 1D05V_S0_NV
VCC_CORE
N11M-GE Power Sequence
VR_CLKEN#
VDD33
Platform CORE_PWRGD
PEX_VDD can ramp up any time
controlled (SYS_PWROK, PCH_PWROK)
PEX_VDD
tNVVDD Sillicon
controlled PM_DRAM_PWRGD
NVVDD
tNV-IFPAB_IOVDD
H_PWRGD
IFPAB_IOVDD
tNV-FBVDDQ PLT_RST#
FBVDDQ
A A
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Title
02_Reference
Size Document Number Rev
A2 LA46 MB -1
Date: Wednesday, January 27, 2010 Sheet 2 of 58
5 4 3 2 1
-1 0107 FOR CO-LAY SLG8LV595
3D3V_S0 3D3V_CK505 1D5V_S0_CK505 1D5V_S0 1D5V_S0_CK505 1D05V_S0 1D05V_CK505
1 2 1 DY 2 -1 0107
R247 1 2
1
1
1
1
1
1
1
0R0603-PAD C358 C347 C348 C369 C346 C383 C349 R264 R268
1
1
1
1
0R3J-0-U-GP 0R0603-PAD C402 C401 C376 C384
1
SC10U10V5ZY-1GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SC47P50V2JN-3GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
2
2
2
2
2
2
SC47P50V2JN-3GP
SC47P50V2JN-3GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SCD1U16V2ZY-2GP
R258
2
2
2
2
D 3D3V_CK505
0R3J-0-U-GP
1D05V_CK505 D
2
Low voltage I/O power
supply for outputs.
VGA 27M RNT1 R75 X1 R79 R80 C107 C131
24
17
29
15
18
1
5
U27
Crystal DY DY Mount Mount Mount Mount Mount
VDD_27
VDD_SRC_IO
VDD_SRC
VDD_CPU_IO
VDD_CPU
VDD_DOT
VDD_REF
CLK GEN Mount Mount DY DY DY DY DY
DY
15 DREFCLK# 4 6 VGA_XIN1_L 4 1 RNT1 VGA_XIN1 55
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