Service Manuals, User Guides, Schematic Diagrams or docs for : LENOVO Laptop Lenovo 3000 N220-N440-Wistron A-note 2.0 Intel
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1 2 3 4 5
SYSTEM DC/DC
Anote2.0 Block Diagram INPUTS
TPS51120
OUTPUTS
38
Project code : 91.4T001.001
5V_S3
Intel CPU
DCBATOUT
3D3V_S5
A
CLK GEN
Meron 2M/4M SV
PCB NO : 06234 SYSTEM DC/DC A
CY28548LFXCT
Revision : -1 ISL6268CAZ 39
3 FSB:667 or 800 MHz
3~6 INPUTS OUTPUTS
Host BUS DCBATOUT 1D05V_S0
667/800MHz SYSTEM DC/DC
UMA solution CRT 17 TPS51116 40
DDRII Slot 1
533/667 15
DDRII 667 Channel A Crestline-GM/PM INPUTS OUTPUTS
S-VIDEOOUT18
AGTL+ CPU I/F DDR I/F DISCRETE solution DCBATOUT
1D8V_S3
0D9V_S0
DDRII Slot 2 DDR II 667 Channel B
INTEGRATED GRAHPICS
533/667 16 LVDS, CRT I/F
8~14
PCIe x16 Nvidia G72MV CHARGER
46~52 14" WXGA LCD ISL6255
19
INPUTS OUTPUTS
B
1394 1394 DMI I/F B
100MHz BT+
28
Ricoh CAMERA DCBATOUT 20V 3.0A
R5C832 5V 100mA
SD/SDIO/MMC PCI
CardReader
MS/MS Pro/xD INTEL BLUE
27
TOOTH CPU DC/DC
ICH8-M USB 2.0 USB x 4 26
ISL6262ACRZ 36,37
INPUTS OUTPUTS
BOARDCOM PCIE 10 USB 2.0/1.1 ports
RJ45
BCM5906/ BCM5787 ETHERNET (10/100/1000Mb)
CONN 31 30
SATA SATA-HDD
25
DCBATOUT VCC_CORE
High Definition Audio
ATA 66/100
PATA ODD
AMOM
C
RJ11 HD Audio
ACPI 1.1
LPC I/F
25
PCB LAYER C
MODEM
CONN
CX20548 PCI/PCI BRIDGE LPC Bus L1: Signal 1
20~23
L2: VCC
HD AUDIO L3: Signal 2
MIC IN CODEC
L4: Signal 3
PCIE x 1
CX20549-12Z PCIE+USB 2.0 KBC
32 WBC8763L L5: GND
Power Switch 55
Ricoh R5538
31
L6: Signal 4
OP AMP
HP
MX4410 34 G-SENSOR
Thermal 53
Mini-Card Flash ROM Touch Int.
New Card & Fan
D 802.11a/b/g/n 1MB 53 Pad 54 KB54 A-NOTE2 D
OP AMP 31 29 G792 24
APA2031 33 Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Block Diagram
2CH SPEAKER Size Document Number Rev
1.5W
A3
Anote2.0 INTEL -1
Date: Thursday, March 22, 2007 Sheet 1 of 56
1 2 3 4 5
A B C D E
INTEL ICH8-M STRAP PIN <21,23> +RTCVCC +RTCVCC
<4,5,6,7,8,11,12,13,21,23,39,56> 1D05V_S0 1D05V_S0
<3,10,12,23,42> 1D25V_S0 1D25V_S0
Signal Usage/When Sampled Comment XOR Chain Entrance Strap <30> 1D2V_LAN_S5 1D2V_LAN_S5
HDA_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 ICH_RSVDtp3 AZ_DOUT_ICH Description
<31,57> 1D5V_NEW _S0 1D5V_NEW _S0
PCIE Port Config 1 bit1, pulled low at rising edge of PWROK.When TP3 not 0 0 RSVD
4 Rising Edge of PWROK pulled low at rising edge of PWROK,sets bit1 of 0
1
1
0
Enter XOR Chain
Normal Operation(default)
4
RPC.PC(Config Registers:offset 224h) 1 1 Set PCIE port cofig bit1
<10,12,13,15,16,40,42,45> 1D8V_S3 1D8V_S3
HDA_SYNC PCIE Port Config 1 bit0, Sets bit0 of RPC.PC(Config Registers:Offset 224h)
Rising Edge of PWROK. <30,31> 2D5V_LAN_S5 2D5V_LAN_S5
GNT2# PCIE Port Config 2 bit0, Sets bit2 of RPC.PC(Config Registers:Offset 224h)
Rising Edge of PWROK.
<21,24,38,44,53,54,55> 3D3V_AUX_S5 3D3V_AUX_S5
GPIO20 Reserved Weak Internal PULL-DOWN.NOTE:This signal should <30,31> 3D3V_LAN_S5 3D3V_LAN_S5
not be pull HIGH.
<3,10,11,12,13,15,16,17,18,19,20,21,22,23,24,25,27,28,29,30,31,32,34,35,36,38,39,41,42,45,46,47,50,52,53,54,55,56,57,58> 3D3V_S0 3D3V_S0
Sampled low:Top-Block Swap mode(inverts A16 for all A16 swap override strap
GNT3# Top-Block Swap Override. cycles targeting FWH BIOS space). <19,20,22,23,26,29,30,31,32,38,40,43,45,53,54,55,56,58> 3D3V_S5 3D3V_S5
Rising Edge of PWROK. Note: Software will not be able to clear the PCI_GNT#3 low = A16 swap override enable
Top-Swap bit until the system is rebooted high = default <29,38,43> 5V_AUX_S5 5V_AUX_S5
without GNT3# being pulled down. BOOT BIOS Strap
PCI_GNT#0 SPI_CS#1 BOOT BIOS Location
GNT0# Boot BIOS Destination Controllable via Boot BIOS Destination bit <17,19,22,23,24,25,33,35,36,39,41,42,45,46,54,56,57> 5V_S0 5V_S0
SPI_CS1# Selection. (Config Registers:Offset 3410h:bit 11:10). 0 1 SPI
Rising Edge of PWROK. GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. 1 0 PCI <23,26,38,40,45,56> 5V_S5 5V_S5
1 1 LPC(Default)
Integrated VccSus1_05 <43,44> AD+ AD+
VccSus1_5 and VccCL1_5 Enables integrated VccSus1_05,VccSus1_5 and integrated VccSus1_05,VccSus1_5,VccCL1_5
INTVRMEN VRM Enable/Disable.Always VccCL1_5 VRM when sampled high <19,36,37,38,39,40,41,43,45,56> DCBATOUT DCBATOUT
SM_INTVRMEN High=Enable Low=Disable
sampled.
<10,15,16,40> DDR_VREF_S3 DDR_VREF_S3
3 Integrated VccLAN1_05 Enables integrated VccLAN1_05,VccCL1_05 VRM
integrated VccLan1_05VccCL1_05 3
LAN100_SLP VccCL1_05 VRM enable when sampled high LAN100_SLP High=Enable Low=Disable
/Disable. Always sampled. <19> LCDVDD_S0 LCDVDD_S0
<5,6,37> VCC_CORE_S0 VCC_CORE_S0
SATALED# PCIE LAN REVERSAL.Rising This signal has weak internal pull-up. DEFAULE HIGH
Edge of PWROK. set bit27 of MPC.LR(Device28:Function0:Offset D8)
If sampled high, the system is strapped to the No Reboot Strap
SPKR No Reboot. "No Reboot" mode(ICH8M will disable the TCO Timer SPKR LOW = Defaule
Rising Edge of PWROK. system reboot feature). The status is readable
via the NO REBOOT bit.(Offset:3410h:bit5)
High=No Reboot
TP3 XOR Chain Entrance.
Rising Edge of PWROK.
This signal should not be pull low unless using
XOR Chain testing. INTEL ICH8-M INTEGRATED
GPIO33/
HDA_DOCK_EN#
Internal Pull-Up.If sampled low,the Flash Descriptor
Flash Descriptor Security Security will be overidden.if high,the Security
Override Strap measures defined in the Flash Descriptor will be in
PULL-UPS and PULL-DOWNS
Rising Edge of PWROK. effect.
8.2K PULL HIGH
This should only be used in manufacturing SIGNAL Resistor Type/Value
environments HDA_BIT_CLK PULL-DOWN 20K
HDA_RST# NONE
HDA_SDIN[3:0] PULL-DOWN 20K
2 HDA_SDOUT PULL-DOWN 20K 2
HDA_SYNC PULL-DOWN 20K
INTEL CRESTLINE STRAP PIN
GNT[3:0] PULL-UP 20K
GPIO[20] PULL-DOWN 20K
CFG Strap LOW 0 HIGH 1 LDA[3:0]#/FHW[3:0]# PULL-UP 20K
CFG 5 LAN_RXD[2:0] PULL-UP 20K
DMI X 2 DMI X 4
CFG 8 LDRQ[0] PULL-UP 20K
Low Power PCI Express Normal Low Power mode
CFG 9 LDRQ[1]/GPIO23 PULL-UP 20K
PCI Express Graphics Lane Reversal Normal Mode(Lanes
Lane Reversal number in order) PME# PULL-UP 20K
CFG 16
FSB Dynamic ODT Disabled Enabled PWRBTN# PULL-UP 20K
CFG 19
DMI Lane Reserved Normal Operation Reserved Lane SATALED# PULL-UP 20K
CFG 20 Only PCIE or SDVO PCIE and SDVO are
Concurrent SDVO/PCIE is operation operation simultaneous SPI_CS1# PULL-UP 20K
SDVO_CTRL_DATA NO SDVO Card SDVO Card Present SPI_CLK PULL-UP 20K
Present
SDVO Present SPI_MOSI PULL-UP 20K
CFG 12 XOR/ALL-Z SPI_MISO PULL-UP 20K
1 CFG 13
A-NOTE2
1
LL(00) Reserved TACH_[3:0] PULL-UP 20K
LH(01)
HL(10)
XOR Mode Enabled
All Z Mode Enabled SPKR PULL-DOWN 20K Wistron Corporation
HH(11) Normal Operation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
TP[3] PULL-UP 20K Taipei Hsien 221, Taiwan, R.O.C.
USB[9:0][P,N] PULL-DOWN 15K Title
CL_RST# TBD Table of Content
Size Document Number Rev
A3
Anote2.0 INTEL -1
Date: Thursday, March 22, 2007 Sheet 2 of 56
A B C D E
3D3V_S0 5 3D3V_S0_CK505 4 3 2 1
L22
1 2
Cypress Setting
MLB-160808-18-GP
SRC0 CLK_MCH_DREFCLK
1
1
1
1
1
1
1
1
C405 C408 C446 C424 C444 C438 C425 C459
3D3V_S0_CK505 1D25V_S0_CK505
SRC1 MCH_SSCDREFCLK
SC1U10V3KX-3GP
SC10U10V5ZY-1GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
2
2
2
2
2
2
2
1
X3
X-14D31818M-30GP
D D
2
1
1
SC33P50V2JN-3GP
C448 C455
SC33P50V2JN-3GP
SC33P50V2JN-3GP
16
46
62
23
19
27
43
52
33
56
U36
2
2
4
9
VDD_REF
VDD_48
VDD_SRC
VDD_CPU
VDD_PLL3
VDD_IO
VDD_PLL3_IO
VDD_SRC_IO
VDD_SRC_IO
VDD_SRC_IO
VDD_CPU_IO
VDD_PCI
61 RN67 1 4 SRN0J-6-GP CLK_CPU_BCLK <4>
1D25V_S0 1D25V_S0_CK505 CPUT0
60 2 3 CLK_CPU_BCLK# <4>
CPUC0
L23 C410 SC4D7P50V2CN-1GP CLK_XTAL_IN 3 58 RN66 1 4 SRN0J-6-GP CLK_MCH_BCLK <8>
CLK_XTAL_OUT XN CPUT1
1 2 2 57 2 3 CLK_MCH_BCLK# <8>
XOUT CPUC1
1 2
MLB-160808-18-GP 54 RN65 1 4 SRN0J-6-GP CPUCLK_ITP_200M <7>
SRCT8/CPU2_ITPT
1
1
1
1
1
1
1
1
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