Service Manuals, User Guides, Schematic Diagrams or docs for : LG LG R590 gigabyte_q1585n_forsa_f7685_quanta_ql4_rev_e_sch
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Dis. & UMA QL4 (15.6W) BLOCK DIAGRAM 01
27MHz
A CPU A
DDRIII 800/1066 MT/s
PAGE 22
DDRIII-SODIMM1 nVIDIA (40nm)
1333MT/s CFD only Auburndale 35W
PAGE 12 Clarksfield 45W Switchable IC
N10M-GE
128 Bit PAGE 22
DDRIII-SODIMM2 DDRIII 800/1066 MT/s N10P-GE
969p PAGE 32~33
1333MT/s CFD only
PAGE 13 PAGE 3~6 PAGE 41~42
PAGE 21
32.768KHz 25MHz
DMI LINK
PAGE 31
B B
14.318MHz
PAGE 31 CLOCK GEN
9LRS3197
PCH PAGE 2
7,10,11
Ibex-M 0,1,2
UMA GPU CORE (RT8152A) 8 9 6
PAGE 32
PAGE 30 PAGE 7~11 PAGE 24 PAGE 24 PAGE 21 PAGE 23
SYSTEM POWER RT8206B
PAGE 33 PCI-E
32.768KHz
VCCP +1.1VTT(RT8208A) AND PCH
1.05V(RT8204)
PAGE 34
C C
AR8131(M)
PAGE 28 PAGE 30 GagaLAN PAGE 27
CPU CORE ISL6288 PAGE 27 PAGE 26
PAGE 35
25MHz
VGACORE(1.025V) RT8208A PAGE 29
PAGE 36
PAGE 26
GMT G9931P1U
PAGE 24
DDR III SMDDR_VTERM
1.5V/1.5VSUS(RT8207) PAGE 29
PAGE 37 PAGE 28 PAGE 31 PAGE 7 PAGE 26
SYSTEM CHARGER(ISL6251AHAZ-T)
PAGE 39
PAGE 25
D D
PAGE 24
PAGE 24 PAGE 25
Size Document Number Rev
Custom E
Block Diagram
1 2 http://laptop-motherboard-schematic.blogspot.com/
3 4 5 6 7
Date: Friday, October 09, 2009 Sheet
8
1 of 44
1 2 3 4 5 6 7 8
+1.05V +VDDIO_CLK
L23
1 2
HCB1608KF-181T15_6 C459
C453
C450
C458
.1U/10V_4
.1U/10V_4
10U/6.3V_6S
10U/6.3V_6S
02
Place each 0.1uF cap as close as CLOCK GENERATOR +3V
possible to each VDD IO pin. Place
the 10uF caps on the VDD_IO plane.
A R303 A
U19 *10K/F_4
+3V
C451 4.7U/6.3V_6 1 23 CLK_BUF_BCLK_P [8] CPU_SEL
C471 4.7U/6.3V_6 VDD_USB CPU-0 133 or 100 Mhz output to PCH
5 VDD_LCD CPU-0# 22 CLK_BUF_BCLK_N [8]
C452 .1U/10V_4 17
C454
C470
.1U/10V_4
.1U/10V_4
24
29
VDD_SRC
VDD_CPU RTM875N- CPU-1 20
19
R306
10K/F_4
C469 .1U/10V_4 VDD_REF CPU-1#
C464 .1U/10V_4
+VDDIO_CLK
632-GRT 3 96Mhz output for generate 48Mhz
DOT96T_LPR CLK_BUF_DREFCLK [8]
18 VDD_CPU_IO DOT96C_LPR 4 CLK_BUF_DREFCLK# [8] ( USB ) and 24 Mhz ( HDA )clk
15 VDD_SRC_IO
[8,12,13,27,30] CGDAT_SMB 31 SDATA SRC-1 13 CLK_BUF_PCIE_3GPLL [8]
[8,12,13,27,30] CGCLK_SMB 32 14 CLK_BUF_PCIE_3GPLL# [8] 100Mhz output for DMI reference clk
SCLK SRC-1#
0 1
+3V R296 10K/F_4 16 10 CLK_BUF_DREFSSCLK [8]
CLK_ICH_14M R300 33_4 CPU_SEL CPU_STOP# SATA 100Mhz output for SATA reference clk
[8] CLK_ICH_14M 30 REF_0/CPU_SEL SATA# 11 CLK_BUF_DREFSSCLK# [8]
C465 10P/50V_4
CK_PW RGD_R 25 6 CLK_VGA_27M_NOSS R308 33_4 CLK_27M_NONSS [16] CPU0/1=133MHz CPU0/1=100MHz
CK_PWRGD/PD#_3.3 27MHz_nonSS CLK_VGA_27M_SS R309 33_4
27MHz_SS 7 CLK_27M_SS [16] CPU_SEL (default)
Place the 33 ohm XTAL_OUT 27
XTAL_IN XOUT
resistors close to the CK 505 28 33
Discrete and Hybrid
9
XIN
VSS_SATA
QFN32 GND
VSS_REF 26
2 VSS_USB VSS_CPU 21
8 VSS_LCD VSS_SRC 12
+3V RTM875N-632-GRT
B B
R295
1K/F_4
CK_PW RGD_R
Y3
XTAL_IN 1 2XTAL_OUT
3
Q10
2N7002E
14.318MHZ
1
1
R297
[37] VR_PW RGD_CLKEN# 2 100K/F_4 C461 C457
33P/50V_4 33P/50V_4
2
2
1
CPU bracket Hole. PAD and HOLE MINI CARD Hole. MDC Hole.
C C
h-tc146bc256d146p2
H21
h-tc146bc256d146p2
H19
H19
1
1
*h-tc295bc220d161p2
H5
*h-tc295bc220d161p2
H6
H6
*h-tc295bc220d161p2
H10
*h-tc295bc220d161p2
H11
*h-ql4-1
H1
*h-c315d106p2
H7
H7
*h-c315d106p2
*h-c315d106p2
H2
*h-ql4-3
H22
*H-C315D106P2
H25
*h-c315d106p2
H15
*h-c315d106p2
H16
H16
*H-tC130bc197d130pb
H18
*O-O236X669D236X669N
H14
H14
h-tc67bc276d67p2
H26
H-TC161BC276D161P2
H30
H-TC161BC276D161P2
H27
H27
h-tc67bc276d67p2
h-tc67bc276d67p2
H29
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
EMI solution.
*h-tc421x335bc315d106p2
H17
*h-c315d106p2
H23
H23
*H-C315D106P2
*H-C315D106P2
H4
*h-ql4-2
H9
B-stage change
*H-C315D130P2
H3
*H-TC130BC197D130PB
*H-TC130BC197D130PB
H24
*h-tc67bc276d67p2
H28
*H-TC161BC276D161P2
H20
H20
B-stage change
1
1
1
1
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