Service Manuals, User Guides, Schematic Diagrams or docs for : LG Laptop LG R480 - QUANTA QL3 Preso-II - REV 1A
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>> Download LG R480 - QUANTA QL3 Preso-II - REV 1A documenatation <<
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1 2 3 4 5 6 7 8
PCB STACK UP
8L
Preso-II BLOCK DIAGRAM 01
CPU CPU THERMAL
LAYER 1 : TOP SENSOR
Penryn 14.318MHz
A LAYER 2 : SGND PAGE 4 A
478P (uPGA)/35W
LAYER 3 : IN1 PAGE 3,4 CLK_CPU_BCLK,CLK_CPU_BCLK#
CLK_MCH_BCLK,CLK_MCH_BCLK# CLOCK GEN
LAYER 4 : SGND1
DREFCLK,DREFCLK# ALPRS355B MLF64PIN
FSB 667/800/1066
LAYER 5 : SVCC DREFSSCLK,DREFSSCLK#
PAGE 2
LAYER 6 : IN2
LAYER 7 : SGND2 PS8101
PAGE 18 27MHz
LAYER 8 : BOT
NORTH BRIDGE
DDRII 667/800 MHz HDMI CON
DDRII-SODIMM1
PAGE 18
PAGE 10,11 Cantiga NVIDIA
PCI-Express
16X
N10M-64bit CRT
DDRII-SODIMM2 DDRII 667/800 MHz
B 533p PAGE 18 B
PAGE 10,11
PAGE 5~9 Dual Link
PAGE 12~16 LCD CONN
32.768KHz PAGE 17
DMI LINK NBSRCCLK, NBSRCCLK#
SATA - HDD
SATA0 150MB USB2.0
PAGE 28 0,1,2 8 9 12MHz 6 7,10,11
SYSTEM CHARGER(ISL6251AHAZ-T) USB2.0 Ports BlueTooth Webcam
SOUTH BRIDGE Mini PCI-E Card x2
PAGE 32 SATA1 150MB X3 PAGE 24 PAGE 29 PAGE 17
SATA - CD-ROM CR for UMA Express Card x1
RTS5159 PAGE 28,31
PAGE 28
SYSTEM POWER ISL6237IRZ-T PAGE 23
ICH9-M
PAGE 33 SATA5 150MB PCI-E
E-SATA
PAGE 31 X2 X1 X1
DDR II SMDDR_VTERM Azalia
C 1.8V/1.8VSUS(TPS51116REGR) PAGE 19,20,21,22 Mini PCI-E Express
C
PAGE 37 LAN
Card Realtek Card
Analog (Wireless LAN PCIE-LAN
VCCP +1.5V AND GMCH
(NEW CARD)
Realtek / Robson) RTL8103EL/8111DL
1.05V(RT8204) 32.768KHz LPC (10/100/GagaLAN) PAGE 28
PAGE 34 ALC272 PAGE 31 PAGE 26,27
MDC CONN
PAGE 25 PAGE 24
VGACORE(1.025V)Oz8118
Keyboard ENE KBC 25MHz
PAGE 36 Touch Pad PAGE 30 AUDIO
Amplifier
KB3926 C0 SPI TPA6017A2
RJ45
CPU CORE ISL6266A PAGE 26
PAGE 20
PAGE 35 PAGE 25
PAGE 30
microphone Audio Jacks Jack to
D D
(Phone/ MIC) Speaker
GMT G9931P1U
PAGE 17 PAGE 24 PAGE 25
SPI
FAN PROJECT : Preso-II
PAGE 29 PAGE 30
Quanta Computer Inc.
Size Document Number Rev
Custom 1A
Block Diagram
NB5 Date: Monday, April 27, 2009 Sheet 1 of 39
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
+3V
02
4,6,9,10,11,12,14,15,17,18,19,20,21,22,24,25,26,28,29,30,31,35,36,38 +3V
3,4,5,6,8,9,19,22,29,34,35 +1.05V
L24
1 2 +3V_CK_MAIN
HCB1608KF-181T15_6
C471 C456 C445 C720 C419 C424
10U/6.3V_8 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4
U12
L39 +3V_CK_MAIN 23 61
VDDPLL3 CPUCLKT0 CLK_CPU_BCLK 3
1 2 +3V_CK_CPU 16 60
A VDD48 CPUCLKC0 CLK_CPU_BCLK# 3 A
HCB1608KF-181T15_6 9
C726 C473 4
VDDPCI
VDDREF
CK505 CPUCLKT1 58 CLK_MCH_BCLK 5
46 VDDSRC CPUCLKC1 57 CLK_MCH_BCLK# 5
10U/6.3V_8 .1U/10V_4 +3V_CK_CPU 62 VDDCPU
CPUT2_ITP/SRCT8 54
+3V_CK_MAIN2 19 53
VDD96I/O CPUC2_ITP/SRCC8
27 VDDPLL3I/O
L23 33 20 SRC0 RP64 4 3 *4P2R-S-0
VDDSRCI/O DOTT_96/SRCT0 DREFCLK 6 UMA
1 2 +3V_CK_MAIN2 43 21 SRC0# 2 1
VDDSRCI/O DOTC_96/SRCC0 DREFCLK# 6
HCB1608KF-181T15_6 52
C479 C423 C718 C420 C434 C475 C476 VDDSRCI/O SRC1
27MHz_Nonss/SRCCLK1/SE1 24
56 25 SRC1# RP46 2 1 4P2R-S-0
VDDCPU_IO 27Mhz_ss/SRCCLC1/SE2 CLK_PCIE_VGA 12
10U/6.3V_8 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 55 4 3 Des
NC CLK_PCIE_VGA# 12
SRCCLKT2/SATACL 28 CLK_PCIE_NEW 28
SRCCLKC2/SATACL 29 CLK_PCIE_NEW# 28
CG_XIN 3
CG_XOUT X1
2 X2 SRCCLKT3/CR#_C 31
SRCCLKC3/CR#_D 32
SRCCLKT4 34 CLK_PCIE_3GPLL 6
R207 *100K/F_4 35
SRCCLKC4 CLK_PCIE_3GPLL# 6
UMA
21 CK_PWG 63 CK_PWRGD/PD# PCI_STOP# 45 PM_STPPCI# 21
CPU_BSEL1 R208 2.2K_4 FSB 64 44 SRC1 RP45 2 1 *4P2R-S-0
FSLB/TEST_MODE CPU_STOP# PM_STPCPU# 21 DREFSSCLK 6
SRC1# 4 3 DREFSSCLK# 6
SRCCLKT6 48 CLK_PCIE_ICH 20
SRCCLKC6 47 CLK_PCIE_ICH# 20
RP63 4 3 4P2R-S-33 27M_NONSS 14
10,11,28,31 CGCLK_SMB 7 SCLK SRCCLKT7/CR#_F 51 CLK_PCIE_WLAN 31 2 1 27M_SS 14
+3V 6 50
B
10,11,28,31 CGDAT_SMB SDATA SRCCLKC7/CR#_E CLK_PCIE_WLAN# 31 B
+3V
Des
SRCCLKT9 37 CLK_PCIE_LAN 26
22 GND SRCCLKC9 38 CLK_PCIE_LAN# 26
2
26 GND
R178 18 41
GND48 SRCCLKT10 CLK_PCIE_SATA 19
59 GNDCPU SRCCLKC10 42 CLK_PCIE_SATA# 19
10K/F_4 R187 15
Q10 GNDPCI
1 40
1
GNDREF SRCCLKT11/CR#_H CLK_PCIE_WWAN 31
2
2N7002 10K/F_4 30 39
GNDSRC SRCCLKC11/CR#_G CLK_PCIE_WWAN# 31
TME 36
CGDAT_SMB GNDSRC
21 PDAT_SMB 3 1 49
GNDSRC
8 R_CLK_NEWCARD_OE# R184 475/F_4
PCICLK0/CR#_A CLK_NEWCARD_OE# 28
0 = overclocking 10 R_CLK_MCH_OE# R180 475/F_4
PCICLK1/CR#_B CLK_MCH_OE# 6
11 TME R175 33_4
of CPU and SRC PCICLK2/TME PCLK_DEBUG 31
R186 12 R_PCLK_KBC R176 33_4
PCICLK3 PCLK_KBC 30
+3V 13 27M_SEL
allowed 10K/F_4 PCICLK4/27_SELECT
Q9 65 ITP_EN R141 33_4
EPAD PCLK_ICH 20
2
1 = overclocking 2N7002
14 R153 22_4
of CPU and SRC PCI_F5/ITP_EN CLK_48M_USB 21
3 1 CGCLK_SMB R154 22_4
21 PCLK_SMB CLK_48M_CR 23
17 FSA R152 2.2K_4 CPU_BSEL0
not allowed USB_48MHZ/FSLA FSC R199 10K/F_4 CPU_BSEL2
5 FSLC R198 33_4
FSLC/TST_SL/REF CLK_14M_ICH 21
RTM875N-606-VD-GR
+3V
C C
2
R150
Des
10K/F_4
1
27M_SEL Y2 +3V
27M_SEL
CG_XIN 1 2 CG_XOUT PIN20 PIN21 PIN24 PIN25
2
PIN13 CK505 QFN64
R151 CLK_MCH_OE# R181 2 1 10K/F_4
14.318MHZ
1
1
UMA C478 C477
*10K/F_4 0=UMA DOT96T DOT96C SRCT1/LCDT_100 SRCT1/LCDT_100 ICS ICS9LPRS355BKLF ALPRS355000
33P/50V_4 33P/50V_4 CLK_NEWCARD_OE# R185 2 1 10K/F_4
1
2
2
Silego SLG8SP513VTR AL8SP513000
1 = External
VGA SRCT0 SRCC0 27Mout-NSS 27Mout-SS Realtek RTM875N-606-VD-GR AL000875000
0 = UMA
1 = External VGA R_PCLK_KBC
PV Modify CPU Clock select
2
+3V CPU_BSEL0 R135 *0_4S R171
3 CPU_BSEL0 MCH_BSEL0 6
FSC FSB FSA CPU SRC PCI *10K/F_4
2
1 0 1 100 100 33
1
R156 R138 *1K/F_4
*10K/F_4 CPU_BSEL1 R471 *0_4S
0 0 1 133 100 33 C436 *33P/50V_4 PCLK_KBC
D 3 CPU_BSEL1 MCH_BSEL1 6 D
0 1 1 166 100 33
1
C408 *27P/50V_4 PCLK_ICH
ITP_EN 0 1 0 200 100 33
+1.05V R473 *1K/F_4 C435 *33P/50V_4 PCLK_DEBUG
2
R155 CPU_BSEL2 R197 *0_4S
0 0 0 266 100 33 C402 10P/50V_4 CLK_48M_USB
3 CPU_BSEL2 MCH_BSEL2 6
10K/F_4
1 0 0 333 100 33 C405 10P/50V_4 CLK_48M_CR
PROJECT : Preso-II
1K to NB only when
1 1 0 400 100 33 Quanta Computer Inc.
1
R213 *1K/F_4 XDP is implement.Non C463 *33P/50V_4 CLK_14M_ICH
+1.05V XDP can use 0 ohm
1 1 1 RSVD 100 33 Size Document Number Rev
Enable ITP CLK For EMI Custom 1A
Clock Generator
NB5 Date: Tuesday, May 05, 2009 Sheet 2 of 39
1 2 3 4 5 6 7 8
5 4 3 2 1
2,4,5,6,8,9,19,22,29,34,35 +1.05V
03
U19A
5 H_A#[35:3] 5 H_D#[63:0] H_D#[63:0]
H_A#3 J4 H1 U19B
D A[3]# ADS# H_ADS# 5 D
H_A#4 L5 E2 H_D#0 E22 Y22 H_D#32
A[4]# BNR# H_BNR# 5 D[0]# D[32]#
ADDR GROUP 0
H_A#5 L4 G5 H_D#1 F24 AB24 H_D#33
A[5]# BPRI# H_BPRI# 5 D[1]# D[33]#
H_A#6 K5 H_D#2 E26 V24 H_D#34
H_A#7 A[6]# H_D#3 D[2]# D[34]# H_D#35
M3 A[7]# DEFER# H5 H_DEFER# 5 G22 D[3]# D[35]# V26
H_A#8 N2 F21 H_D#4 F23 V23 H_D#36
A[8]# DRDY# H_DRDY# 5 D[4]# D[36]#
H_A#9 J1 E1 H_D#5 G25 T22 H_D#37
A[9]# DBSY# H_DBSY# 5 D[5]# D[37]#
H_A#10 N3 H_D#6 E25 U25 H_D#38
A[10]# D[6]# D[38]#
DATA GRP 0
DATA GRP 2
DATA GRP 2
H_A#11 P5 F1 H_D#7 E23 U23 H_D#39
A[11]# BR0# HBREQ#0 5 D[7]# D[39]#
H_A#12 P2 H_D#8 K24 Y25 H_D#40
A[12]# D[8]# D[40]#
CONTROL
CONTROL
H_A#13 L2 D20 H_IERR# R23 49.9/F_4 +1.05V H_D#9 G24 W22 H_D#41
H_A#14 A[13]# IERR# H_D#10 D[9]# D[41]# H_D#42
P4 A[14]# INIT# B3 H_INIT# 19 J24 D[10]# D[42]# Y23
H_A#15 P1 H_D#11 J23 W24 H_D#43
H_A#16 A[15]# H_D#12 D[11]# D[43]# H_D#44
R1 A[16]# LOCK# H4 H_LOCK# 5 H22 D[12]# D[44]# W25
M1 H_D#13 F26 AA23 H_D#45
5 H_ADSTB#0 ADSTB[0]# H_CPURST# 5 D[13]# D[45]#
C1 H_D#14 K22 AA24 H_D#46
5 H_REQ#[4:0] RESET# D[14]# D[46]#
H_REQ#0 K3 F3 H_RS#0 H_D#15 H23 AB25 H_D#47
H_REQ#1 REQ[0]# RS[0]# H_RS#1 D[15]# D[47]#
H2 REQ[1]# RS[1]# F4 5 H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 5
H_REQ#2 K2 G3 H_RS#2 H_RS#[2:0] 5 H26 AA26
REQ[2]# RS[2]# 5 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 5
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