Service Manuals, User Guides, Schematic Diagrams or docs for : Quanta Quanta_DO1
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5 4 3 2 1
DO1 BLOCK DIAGRAM 01
YONAH+CALISTOGA+ICH_7
D D
Yonah / Merom
Clock Generator
479 Pins CPU Thermal ICS954226AG
(Micro-FCPGA) Sensor IDT CV111
PG 13
GMT781 PG 25
PG 4,5
FSB
533/667MHZ
S_VEDIO
PG 18 DDR2 INTERFACE, 533/667 MHz
Calistoga DDR-SODIMM1 PG 12
C LCD Panel L007 LVDS C
PG 19 PG 28
1466 LGA
CRT port DDR-SODIMM2 PG 12
PG 18
R.G,B PG 6~11
DMIx4
SATA interface PCI-Express
SATA HDD
PG 27
ICH7-M 33MHZ, 3.3V PCI BUS
SATA interface
SATA HDD 652 BGA
PG 27
MINI-PCI E LAN
Primary IDE - ODD PATA 66/100 SOCKET BCM5751M
B B
PG 27 CARDBUS PG 24
PG 14,15,16,17 PG 23
USB 2.0 R5C841
USB PORT 0,1 PG 20,21
PG 26
USB PORT 2,3 RJ45
CPU CORE PG 30 PG 26
Azalia PG 23
3.3V LPC, 33MHz
GMCHVTT & VCC1.5 USB PORT 4
PG 31 PG 26 MDC Audio
V1.5
PG 29 PG 30
DC/DC 3V & 5V
PG 32 PC87541 FAN 1
USB PORT 5 PG 25
TV MODULE PG 25 176 Pins LQFP
1.8V/0.9V/2.5V
A PG 33 USB PORT 6 A
PG 22 RJ11
New card PG 21
BATT CHARGER & QUANTA
AC CONNECTOR PG 34 USB PORT 7
Title
COMPUTER
Fingerprinter PG 25 TouchPAD Keyboard FLASH System Block Diagram
BATT CONNECTOR PG 25 PG 26 PG 22 Size Document Number Rev
Custom 3C
PG 35 DO1
Date: Thursday, February 09, 2006 Sheet 1 of 39
5 4 3 2 1
5 4 3 2 1
1. Schematic Page Description : 02
DO1 Schematic Ver : 0.2 31. AMP for Speaker
1. Block Diagram 16. ICH7-M GPIO/SMB
D 2. Schematic Page List 17. ICH7-M POWER/GND 32. CPU CORE D
3. System Info 18. CRT Port / S-VIDEO 33. VCC1.5V / GMCHVTT
4. u-FCPGA Yonah (1/2) 19. LCD CNN / LID / Audio board CONN 34. DC/DC 3V,5V POWER
5. u-FCPGA Yonah (2/2) 20. R5C841 CONTROLLER 35. 1.8V / 0.9V DDR2 / VCC2.5
6. Calistoga HOST 21. R5C841 CNN & 4 IN 1 36. Battery Charge Circuit
7. Calistoga DDR II 22. PC87541L / BIOS 37. Battery Select
8. Calistoga VGA/DMI/NCTF 23. LAN MARVELL 88E8055/RJ45 CONN
9. Calistoga POWER 24. Mini PCIE
10. Calistoga POWER 25. FAN/THERMAL/SWICH CONN/BEEP/TOUCH PAD/ IR RECEIVER
11. Calistoga GND 26. USB K/B CNN
12. DDR II SODIMM CNN 27. SATA / PATA HDD
13. Clock Generator 28. L007
14. ICH7-M CPU/IDE/SATA/AC97/LPC 29. MDC1.5
C C
15. ICH7-M USB/DMI/LPC/PCI_E/PCI 30. CODEC ALC262
2. PCI Description :
IDSEL CHIP PCIINT CHIP BUSMASTER
REQ CHIP
AD25 CardBus (R5C841) IRQA CardBus
REQ0 / GNT0
B IRQB CardBus B
REQ1 / GNT1 CardBus (R5C841)
IRQC CardBus
REQ2 / GNT2
IRQD
REQ3 / GNT3
IRQE
REQ4 / GNT4
IRQF
SM BUS Block Diagram
DDR2
Battery
CLK GEN
EC (KBC) EEPROM
ICH7
A A
Express card
SW Thermal QUANTA
Mini PCIE
Title
COMPUTER
Description
Size Document Number Rev
C 3C
DO1
Date: Thursday, February 09, 2006 Sheet 2 of 39
5 4 3 2 1
5 4 3 2 1
Board Stack up Description Voltage Rails 03
PCB Layers Voltage Rails ON S0~S2 ON S3 ON S4 ON S5 Control signal
VCC_CORE Core voltage for Processor X GMCHPG
GMCH_VTT Core voltage for CPU / NB X VR_ON
Layer 1 TOP(FSB,DDR2,CLK,PEG,Component)
SMDDR_VREF 0.9V for DDR2 Termination voltage X MAINON
Layer 2 Ground Plane
D D
Layer 3 IN1(FSB,CLOCK,DDR2,PEG,CLK)
Layer 4 IN2(PCI,IDE,LPC)
RVCC3 X X X RVCCD
Layer 5 Power Plane
Layer 6 BOTTOM, (Component,Other)
VCC1.5 X MAINON
VCC1.8 X MAINON
VCC2.5 X MAINON
VCC3 X MAIND
VCC5 X MAIND
Power On Sequencing Timing Diagram
1.8VSUS X X SUSON
VID 3VSUS X X SUSD
Tsft_star_vcc 5VSUS X X SUSD
VR_ON
Vboot Vid
Tboot
Vcc-core Tboot-vid-tr 3VPCU X X X X VL
Tcpu_up 5VPCU X X X X VL
CPU_UP
C
9VPCU X X X X 5VPCU C
Vccp
Vccp_UP Tvccp_up
Vccgmch
GMCHPWRGD Tgmch_pwrgd ACIN POWER ON TIMING
CLK_ENABLE# ACIN
IMVP4_PWRGD Tcpu_pwrgd 5VPCU/3VPCU
NBSWON#
PWRBTN# To ICH6
RCVV_ON
To ICH6
RSMRST#
Dothan Power-up Timing
Specifications SUSB#,SUSC# From ICH6
Td
SUSON From 87591
B RESET# B
MAINON From 87591
VSUS,VCC
BCLK From 87591
VR_ON
Tc
GMCH_VTT/1.05V
Te
PWRGOOD VCORE_CPU
CK410_PWRGD
Tf To clock generator
Ta Tb
99ms < t 214
VCC PWROK/IMVP_PWRGD
Vcc,boot PLTRST#\PCIRST#
VID[5:0] To GMCH/other PCI device
From ICH6 to CPU
VTT H_PWRGD
H_CPURST#
2ms
Ta=VCC and VCCP asseration to VID[5:0] vaild
Tb=VID[5:0] stable to VCC vaild
Tc=BCLK stable to PWRGOOD assertion Form GMCH to CPU
Td=PWRGOOD to RESET# de-assertion time
A Te=Vcc,boot vaild to PWRGOOD assertion time A
Tf=VCC vaild to PWRGOOD assertion time
QUANTA
Title
COMPUTER
INFORMATION
Size Document Number Rev
C DO1 3C
Date: Thursday, February 09, 2006 Sheet 3 of 39
5 4 3 2 1
5 4 3 2 1
T51
6 H_A#[31:3]
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
J4
L4
M3
K5
M1
U4A
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
ADS#
BNR#
BPRI#
DEFER#
H1
E2
G5
H5
H_ADS#
H_BNR#
H_BPRI#
H_DEFER# 6
6
6
6
GMCH_VTT
GMCH_VTT 5,6,9,10,13,14,17,33
04
ADDR GROUP 0
ADDR GROUP 0
H_A#8 N2 F21
A[8]# DRDY# H_DRDY# 6
H_A#9 J1 E1 R274
A[9]# DBSY# H_DBSY# 6
CONTROL
H_A#10 N3 56
H_A#11 A[10]#
P5 A[11]# BR0# F1 H_BREQ#0 6
D H_A#12 D
P2 A[12]#
H_A#13 L1 D20
A[13]# IERR# 6 H_D#[63:0] H_D#[63:0] 6
H_A#14 P4 B3
A[14]# INIT# H_INIT# 14
H_A#15 P1 T31 U4B
H_A#16 A[15]# H_D#0 E22 H_D#32
R1 A[16]# LOCK# H4 H_LOCK# 6 D[0]# D[32]# AA23
L2 H_D#1 F24 AB24 H_D#33
6 H_ADSTB#0 ADSTB[0]# H_CPURST# 6 D[1]# D[33]#
B1 H_D#2 E26 V24 H_D#34
6 H_REQ#[4:0] RESET# D[2]# D[34]#
H_REQ#0 K3 F3 H_RS#0 H_D#3 H22 V26 H_D#35
REQ[0]# RS[0]# D[3]# D[35]#
DATA GRP 0
H_REQ#1 H2 H_RS#1 H_D#4 F23 H_D#36
DATA GRP 2
REQ[1]# RS[1]# F4 D[4]# D[36]# W25
H_REQ#2 K2 G3 H_RS#2 H_RS#[2:0] 6 H_D#5 G25 U23 H_D#37
H_REQ#3 J3 REQ[2]# RS[2]# H_D#6 E25 D[5]# D[37]# H_D#38
REQ[3]# TRDY# G2 H_TRDY# 6 D[6]# D[38]# U25
H_REQ#4 L5 T55 H_D#7 E23 U22 H_D#39
REQ[4]# H_D#8 K24 D[7]# D[39]# H_D#40
6 H_A#[31:3] HIT# G6 H_HIT# 6 D[8]# D[40]# AB25
H_A#17 Y2 E4 H_D#9 G24 W22 H_D#41
A[17]# HITM# H_HITM# 6 D[9]# D[41]#
H_A#18 U5 H_D#10 J24 Y23 H_D#42
H_A#19 A[18]# H_D#11 J23 D[10 D[42]# H_D#43
R3 A[19]# BPM[0]# AD4 D[11]# D[43]# AA26
H_A#20 W6 AD3 H_D#12H26 Y26 H_D#44
A[20]# BPM[1]# GMCH_VTT D[12]# D[44]#
XDP/ITP SIGNALS
H_A#21 U4 AD1 H_D#13 F26 Y22 H_D#45
H_A#22 A[21]# BPM[2]# H_D#14 K22 D[13]# D[45]# H_D#46
Y5 A[22]# BPM[3]# AC4 D[14]# D[46]# AC26
H_A#23 U2 AC2 H_D#15H25 AA24 H_D#47
H_A#24 A[23]# PRDY# R231 54.9 D[15]# D[47]#
R4 A[24]# PREQ# AC1 6 H_DSTBN#0 H23 DSTBN[0]# DSTBN[2]# W24 H_DSTBN#2 6
H_A#25 T5 AC5 R237 54.9 G22 Y25
A[25]# TCK 6 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 6
H_A#26 T3 AA6 R228 54.9 J26 V23
A[26]# TDI 6 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 6
H_A#27 W3 AB3 R230 54.9
C A[27]# TDO 6 H_D#[63:0] H_D#[63:0] 6 C
H_A#28 W5 AB5 R229 54.9
H_A#29 A[28]# TMS R241 54.9 H_D#16N22 H_D#48
Y4 A[29]# TRST# AB6 D[16]# D[48]# AC22
H_A#30 W2 C20 H_D#17 K25 AC23 H_D#49
A[30]# DBR# XDP_DBRESET# 16 D[17]# D[49]#
H_A#31 Y1 H_D#18 P26 AB22 H_D#50
A[31]# H_PROCHOT# H_D#19R23 D[18]# D[50]# H_D#51
6 H_ADSTB#1 V4 ADSTB[1]# PROCHOT D21 H_PROCHOT# 32 D[19]# D[51]# AA21
DATA GRP 1
H_D#20 L25 H_D#52
DATA GRP 3
THERMDA A24 H_THERMDA 25 D[20]# D[52]# AB21
THERM
A6 A25 H_D#21 L22 AC25 H_D#53
14 H_A20M# A20M# THERMDC H_THERMDC 25 D[21]# D[53]#
A5 H_D#22 L23 AD20 H_D#54
14 H_FERR# FERR# D[22]# D[54]#
C4 C7 H_D#23M23 AE22 H_D#55
14 H_IGNNE# IGNNE# THERMTRIP# PM_THRMTRIP# 8,14 D[23]# D[55]#
H_D#24 P25 AF23 H_D#56
R238 0 H_D#25 P22 D[24]# D[56]# H_D#57
14 H_STPCLK# D5 STPCLK# D[25]# D[57]# AD24
C6 T19 H_D#26 P23 AE21 H_D#58
H CLK
14 H_INTR LINT0 GMCH_VTT D[26]# D[58]#
14 H_NMI B4 A22 H_D#27 T24 AD21 H_D#59
LINT1 BCLK[0] CLK_CPU_BCLK 13 D[27]# D[59]#
14 H_SMI# A3 A21 H_D#28R24 AE25 H_D#60
SMI# BCLK[1] CLK_CPU_BCLK# 13 D[28]# D[60]#
H_D#29 L26 AF25 H_D#61
T4 TP_A32# T20 H_D#30 T25 D[29]# D[61]# H_D#62
AA1 RSVD[01]# D[30]# D[62]# AF22
T6 TP_A33# AA4 T22 TP_EXTBREF T68 H_D#31N24 AF26 H_D#63
T5 TP_A34# RSVD[02]# RSVD[12]# R299 D[31]# D[63]#
AB2 RSVD[03]# 6 H_DSTBN#1 M24 DSTBN[1]# DSTBN[3]# AD23 H_DSTBN#3 6
T3 TP_A35# 1K/F
RESERVED
AA3 RSVD[04]# 6 H_DSTBP#1 N25 DSTBP[1]# DSTBP[3]# AE24 H_DSTBP#3 6
T57 TP_A36# M4 D2 TP_SPARE0 T53 M26 AC20
RSVD[05]# RSVD[13]# 6 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 6
T58 TP_A37# N5 F6 TP_SPARE1 T59
T2 TP_A38# RSVD[06]# RSVD[14]# TP_SPARE2 T56 27.4 R302
T2 RSVD[07]# RSVD[15]# D3 AD26 GTLREF COMP[0] R26
T1 TP_A39# V3 C1 TP_SPARE3 T50 MISC U26 54.9 R301
T52 TP_APM0# RSVD[08]# RSVD[16]# TP_SPARE4 T7 COMP[1] 27.4 R233
B B2 RSVD[09]# RSVD[17]# AF1 COMP[2] U1 B
T54 TP_APM1# TP_SPARE5 T71 R285 *1K 54.9 R232
C3 RSVD[10]# RSVD[18]# D22 C26 TEST1 COMP[3] V1
C23 TP_SPARE6 T78
T18 TP_HFPLL RSVD[19]# TP_SPARE7 T77 R291 51
B25 RSVD[11]# RSVD[20]# C24 D25 TEST2 DPRSTP# E5 R236 0
ICH_DPRSTP# 14
R293 B5
DPSLP# H_DPSLP# 14
PZ47903-2741-01 D24
DPWR# H_DPWR# 6
2K/F B22 D6
13 CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGD 14
13 CPU_BSEL1 B23 BSEL[1] SLP# D7 H_CPUSLP# 6,14
GMCH_VTT C21 AE6
13 CPU_BSEL2 BSEL[2] PSI# PSI# 32
H_PROCHOT# R304 75 PZ47903-2741-01
Layout note: 0.5" max for GTLREF
QUANTA
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