Service Manuals, User Guides, Schematic Diagrams or docs for : Quanta Quanta_R22-HP_Pavilion_G4_G6_G7_REV_1A
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1 2 3 4 5 6 7 8
R22 SYSTEM DIAGRAM 01
DDR3-SODIMM1 DDR3 channel A
AMD Champlain CPU THERMAL
PAGE 6 SENSOR
35mm X 35mm
A A
S1G4 Processor PAGE 5
DDR3-SODIMM2 DDR3 channel B
638P (PGA)35W/25W
PAGE 7 PAGE 3,4,5
HT3
PCI-Express 8X
PCI-E HDMI
PAGE 25
X1 X1 X1 NORTH BRIDGE ATI
CRT
Flash Media LAN Mini PCI-E RS880M A12 PAGE 24 SEYMOUR-XT
RTS5219-GR Realtek Card
PAGE 26 PCIE-LAN
RTS8165EH-CG (Wireless LAN)
21mm X 21mm, 528pin BGA LVDS
B
(10/100) 23mm X 23mm B
PAGE 23
Side port
PAGE 30 PAGE 33 DDR3
PAGE 17,18,19
PAGE 8,9,10,11 20,21
DDR3 RAM
VRAM
for UMA only PAGE 22
RJ45 PAGE 8
ALINK X4
PAGE 30
SYSTEM CHARGER(ISL6251) USB2.0
PAGE 40 0,5,8 15 2 10
SATA - HDD
SATA0 150MB
SOUTH BRIDGE USB2.0 Ports BT softbreeze Webcam
PAGE 29 PAGE 29 PAGE 29
PCI-E WLAN Card x1
SYSTEM POWER ISL6237 X3 X1 PAGE 23 PAGE 33
PAGE 34 SB820 A13
SATA - CD-ROM
SATA4 150MB
21mm X 21mm, 605pin FCBGA
DDR II SMDDR_VTERM PAGE 29
1.8V/1.8VSUS(RT8207) 4.5W(Ext)
C PAGE 37 4.3W(Int) Azalia C
PAGE 12,13,14,15,16
VCCP +1.1V AND +1.2V(RT8204)
PAGE 35 IDT
92HD80
LPC
VGACORE(1.1V~1.2V)Oz8118 PAGE 27
PAGE 38
ENE KBC
AUDIO CONN
CPU CORE ISL6265HRTZ-T KB3930 Qx DIG MIC
(Phone/ MIC)
PAGE 36
PAGE 32 PAGE 27 PAGE 28
SMBUS TABLE
Clock gen/Robson/TV tuner
SB--SCL0/SD0 /DDR2/DDR2 thermal/Accelerometer +3V
D Keyboard PAGE 31 FAN SPI D
Touch Pad PAGE 31
epress card PAGE 28 PAGE 31
Wlan Card +3VS5
PROJECT : R22
EC --SCL/SD Battery charge/discharge +3VPCU Quanta Computer Inc.
EC--SCL2/SD2 VGA thermal/system thermal +3V Size Document Number Rev
Custom 1A
Block Diagram
NB5/RD2
Date: Wednesday, September 15, 2010 Sheet 1 of 43
1 2 3 4 5 6 7 8
5 4 3 2 1
02
D D
Use internal CLK GEN
C C
B B
A A
PROJECT : R22
Quanta Computer Inc.
Size Document Number Rev
Custom 1A
Clock Generator
NB5/RD2
Date: Wednesday, September 15, 2010 Sheet 2 of 43
5 4 3 2 1
5 4 3 2 1
PBY201209T-221Y-N H_THRMDC
03
+CPUVDDA
W/S= 15 mil/20mil H_THRMDA
H_THRMDC 5
+2.5V H_THRMDA 5
VLDT use 1.5A Max current L31 CPU CLK CPU_PWRGD 300_4 R148
+1.1V +1.1V_VLDT C414 LS0805-100M-N C386 C319 C322 CPUCLKP CPU_LDT_RST# 300_4 R149
12 CPUCLKP
4.7U/6.3V_6 4.7U/6.3V_6 0.22U/25V_6 3300P/50V_4 CPUCLKN CPU_LDT_STOP# 300_4 R177
12 CPUCLKN
R174 *0_6/S CPU_LDT_REQ#_CPU *300/F_4 R147 +1.5V
Keep trace from resisor to CPU within 0.6"
+1.1V +1.1V_VLDT_R +CPUVDDA 250mA
keep trace from caps to CPU within 1.2" U19D
R54 *0_6/S U19A W/S= 15 mil/20mil
+CPUVDDA F8 M11
+1.1V_VLDT +1.1V_VLDT_R 10U/6.3V_8 C111 CPUCLKIN R150 169/F_4 CPUCLKIN# +CPUVDDA VDDA1 VSS
D1 VLDT_A0 HT LINK VLDT_B0 AE2 F9 VDDA2 RSVD11 W18
C389 10U/6.3V_8 +1.1V_VLDT D2 AE3 +1.1V_VLDT_R 0.22U/6.3V_4 C126
D C385 0.22U/6.3V_4 +1.1V_VLDT VLDT_A1 VLDT_B1 +1.1V_VLDT_R 180P/50V_4 C133 CPUCLKP C395 3900P/25V_4 CPUCLKIN CPU_SVC_R D
D3 VLDT_A2 VLDT_B2 AE4 A9 CLKIN_H SVC A6
C383 180P/50V_4 +1.1V_VLDT D4 AE5 +1.1V_VLDT_R 10U/6.3V_8 C548 CPUCLKN C394 3900P/25V_4 CPUCLKIN# A8 A4 CPU_SVD_R
VLDT_A3 VLDT_B3 CLKIN_L SVD
HT_NB_CPU_CAD_H0 E3 AD1 HT_CPU_NB_CAD_H0 CPU_LDT_RST# B7
L0_CADIN_H0 L0_CADOUT_H0 12 CPU_LDT_RST# RESET_L
HT_NB_CPU_CAD_L0 E2 AC1 HT_CPU_NB_CAD_L0 CPU_PWRGD A7
L0_CADIN_L0 L0_CADOUT_L0 12 CPU_PWRGD PWROK
HT_NB_CPU_CAD_H1 E1 AC2 HT_CPU_NB_CAD_H1 CPU_LDT_STOP# F10 AF6 CPU_THERMTRIP_L#
L0_CADIN_H1 L0_CADOUT_H1 10,12 CPU_LDT_STOP# LDTSTOP_L THERMTRIP_L
HT_NB_CPU_CAD_L1 F1 AC3 HT_CPU_NB_CAD_L1 CPU_LDT_REQ#_CPU C6 AC7 CPU_PROCHOT_L#
HT_NB_CPU_CAD_H2 L0_CADIN_L1 L0_CADOUT_L1 HT_CPU_NB_CAD_H2 LDTREQ_L PROCHOT_L CPU_MEMHOT_L#
G3 AB1 AA8 T10
HT_NB_CPU_CAD_L2 L0_CADIN_H2 L0_CADOUT_H2 HT_CPU_NB_CAD_L2 CPU_SIC MEMHOT_L
G2 L0_CADIN_L2 L0_CADOUT_L2 AA1 5 CPU_SIC AF4 SIC
HT_NB_CPU_CAD_H3 G1 AA2 HT_CPU_NB_CAD_H3 SideBand Temp sense I2C CPU_SID AF5
HT_NB_CPU_CAD_H[15..0] L0_CADIN_H3 L0_CADOUT_H3 5 CPU_SID SID
HT_NB_CPU_CAD_L3 H1 AA3 HT_CPU_NB_CAD_L3 CPU_ALERT AE6 W7 H_THRMDC
8 HT_NB_CPU_CAD_H[15..0] L0_CADIN_L3 L0_CADOUT_L3 5 CPU_ALERT ALERT_L THERMDC
HT_NB_CPU_CAD_H4 J1 W2 HT_CPU_NB_CAD_H4 W8 H_THRMDA
HT_NB_CPU_CAD_L[15..0] HT_NB_CPU_CAD_L4 L0_CADIN_H4 L0_CADOUT_H4 HT_CPU_NB_CAD_L4 R81 44.2/F_4 CPU_HTREF0 THERMDA
K1 W3 R6
8 HT_NB_CPU_CAD_L[15..0] HT_NB_CPU_CAD_H5 L0_CADIN_L4 L0_CADOUT_L4 HT_CPU_NB_CAD_H5 +1.5VSUS R83 44.2/F_4 CPU_HTREF1 HT_REF0
L3 L0_CADIN_H5 L0_CADOUT_H5 V1 +1.1V_VLDT P6 HT_REF1
HT_NB_CPU_CLK_H[1..0] HT_NB_CPU_CAD_L5 L2 U1 HT_CPU_NB_CAD_L5 place them to CPU within 1.5"
8 HT_NB_CPU_CLK_H[1..0] HT_NB_CPU_CAD_H6 L0_CADIN_L5 L0_CADOUT_L5 HT_CPU_NB_CAD_H6 VDDIO_FB_H
L1 U2 36 CPU_VDD0_RUN_FB_H F6 W9 VDDIO_FB_H 37
HT_NB_CPU_CLK_L[1..0] HT_NB_CPU_CAD_L6 L0_CADIN_H6 L0_CADOUT_H6 HT_CPU_NB_CAD_L6 VDD0_FB_H VDDIO_FB_H VDDIO_FB_L
8 HT_NB_CPU_CLK_L[1..0] M1 L0_CADIN_L6 L0_CADOUT_L6 U3 36 CPU_VDD0_RUN_FB_L E6 VDD0_FB_L VDDIO_FB_L Y9 VDDIO_FB_L 37
HT_NB_CPU_CAD_H7 N3 T1 HT_CPU_NB_CAD_H7 R169
HT_NB_CPU_CTL_H[1..0] HT_NB_CPU_CAD_L7 L0_CADIN_H7 L0_CADOUT_H7 HT_CPU_NB_CAD_L7
N2 R1 36 CPU_VDD1_RUN_FB_H Y6 H6 CPU_VDDNB_RUN_FB_H 36
8 HT_NB_CPU_CTL_H[1..0] HT_NB_CPU_CAD_H8 L0_CADIN_L7 L0_CADOUT_L7 HT_CPU_NB_CAD_H8 510/F_4 VDD1_FB_H VDDNB_FB_H
E5 L0_CADIN_H8 L0_CADOUT_H8 AD4 36 CPU_VDD1_RUN_FB_L AB6 VDD1_FB_L VDDNB_FB_L G6 CPU_VDDNB_RUN_FB_L 36
HT_NB_CPU_CTL_L[1..0] HT_NB_CPU_CAD_L8 F5 AD3 HT_CPU_NB_CAD_L8
8 HT_NB_CPU_CTL_L[1..0] HT_NB_CPU_CAD_H9 L0_CADIN_L8 L0_CADOUT_L8 HT_CPU_NB_CAD_H9 CPU_DBRDY
F3 L0_CADIN_H9 L0_CADOUT_H9 AD5 G10 DBRDY
HT_CPU_NB_CAD_H[15..0] HT_NB_CPU_CAD_L9 F4 AC5 HT_CPU_NB_CAD_L9 CPUTEST25H CPU_TMS AA9 E10 CPU_DBREQ#
8 HT_CPU_NB_CAD_H[15..0] HT_NB_CPU_CAD_H10 L0_CADIN_L9 L0_CADOUT_L9 HT_CPU_NB_CAD_H10 CPU_TCK TMS DBREQ_L
G5 AB4 AC9
HT_CPU_NB_CAD_L[15..0] HT_NB_CPU_CAD_L10 L0_CADIN_H10 L0_CADOUT_H10 HT_CPU_NB_CAD_L10 CPUTEST25L CPU_TRST# TCK CPU_TDO
H5 AB3 AD9 AE9
8 HT_CPU_NB_CAD_L[15..0] HT_NB_CPU_CAD_H11 L0_CADIN_L10 L0_CADOUT_L10 HT_CPU_NB_CAD_H11 CPU_TDI TRST_L TDO
H3 AB5 AF9
HT_CPU_NB_CLK_H[1..0] HT_NB_CPU_CAD_L11 L0_CADIN_H11 L0_CADOUT_H11 HT_CPU_NB_CAD_L11 R168 TDI
H4 AA5
8 HT_CPU_NB_CLK_H[1..0] HT_NB_CPU_CAD_H12 L0_CADIN_L11 L0_CADOUT_L11 HT_CPU_NB_CAD_H12 CPUTEST23
K3 Y5 T4 AD7 J7
HT_CPU_NB_CLK_L[1..0] HT_NB_CPU_CAD_L12 L0_CADIN_H12 L0_CADOUT_H12 HT_CPU_NB_CAD_L12 510/F_4 TEST23 TEST28_H
K4 W5 H8
8 HT_CPU_NB_CLK_L[1..0] HT_NB_CPU_CAD_H13 L0_CADIN_L12 L0_CADOUT_L12 HT_CPU_NB_CAD_H13 CPUTEST18 TEST28_L
L5 V4 T24 H10
C HT_CPU_NB_CTL_H[1..0] HT_NB_CPU_CAD_L13 L0_CADIN_H13 L0_CADOUT_H13 HT_CPU_NB_CAD_L13 CPUTEST19 TEST18 CPUTEST17 C
8 HT_CPU_NB_CTL_H[1..0] M5 L0_CADIN_L13 L0_CADOUT_L13 V3 T27 G9 TEST19 TEST17 D7 T45
HT_NB_CPU_CAD_H14 M3 V5 HT_CPU_NB_CAD_H14 E7 CPUTEST16
HT_CPU_NB_CTL_L[1..0] L0_CADIN_H14 L0_CADOUT_H14 TEST16 T40
HT_NB_CPU_CAD_L14 M4 U5 HT_CPU_NB_CAD_L14 CPUTEST25H E9 F7 CPUTEST15
8 HT_CPU_NB_CTL_L[1..0] L0_CADIN_L14 L0_CADOUT_L14 TEST25_H TEST15 T26
HT_NB_CPU_CAD_H15 N5 T4 HT_CPU_NB_CAD_H15 CPUTEST25L E8 C7 CPUTEST14
L0_CADIN_H15 L0_CADOUT_H15 TEST25_L TEST14 T49
HT_NB_CPU_CAD_L15 P5 T3 HT_CPU_NB_CAD_L15 place them to CPU within 1.5"
L0_CADIN_L15 L0_CADOUT_L15 CPUTEST21 AB8 TEST21 TEST7 C3
HT_NB_CPU_CLK_H0 J3 Y1 HT_CPU_NB_CLK_H0 CPUTEST20 AF7 K8 R163 *300/F_4 +1.1V_VLDT
L0_CLKIN_H0 L0_CLKOUT_H0 T108 TEST20 TEST10
HT_NB_CPU_CLK_L0 J2 W1 HT_CPU_NB_CLK_L0 CPUTEST24 AE7
HT_NB_CPU_CLK_H1 L0_CLKIN_L0 L0_CLKOUT_L0 HT_CPU_NB_CLK_H1 CPUTEST22 TEST24
J5 Y4 +1.5VSUS T5 AE8 C4
HT_NB_CPU_CLK_L1 L0_CLKIN_H1 L0_CLKOUT_H1 HT_CPU_NB_CLK_L1 R375 300/F_4 CPU_DBREQ# CPUTEST12 TEST22 TEST8 CPUTEST29H
K5 Y3 T3 AC8 T46
L0_CLKIN_L1 L0_CLKOUT_L1 CPUTEST27 TEST12
AF8
HT_NB_CPU_CTL_H0 HT_CPU_NB_CTL_H0 R310 1K/F_4 CPUTEST27 TEST27 R116
N1 R2 C9
HT_NB_CPU_CTL_L0 L0_CTLIN_H0 L0_CTLOUT_H0 HT_CPU_NB_CTL_L0 R160 *0_4/S TEST29_H
P1 R3 C2 C8
HT_NB_CPU_CTL_H1 L0_CTLIN_L0 L0_CTLOUT_L0 HT_CPU_NB_CTL_H1 R309 *300/F_4 TEST9 TEST29_L 80.6/F_4
P3 L0_CTLIN_H1 L0_CTLOUT_H1 T5 AA6 TEST6
HT_NB_CPU_CTL_L1 P4 R5 HT_CPU_NB_CTL_L1 CPUTEST29L
L0_CTLIN_L1 L0_CTLOUT_L1 T50
A3 H18
RSVD1 RSVD10
FOX PZ63826-284R-41F A5
RSVD2 RSVD9
H19
DG0^8000004 IC SOCKET SMD 638P S1(P1.27,H3.2) SOCKET_638_PIN B3 AA7 Route as 80ohm, diff
RSVD3 RSVD8
MLX 47296-4131 B5 D5
RSVD4 RSVD7
C1 RSVD5 RSVD6 C5
DG0^8000003 IC SOCKET SMD 638P S1(P1.27,H3.2)
TYC 4-1903401-2
DG0^8000005 IC SOCKET SMD 638P S1(P1.27,H3.2) SOCKET_638_PIN
+1.5VSUS
CN4
20
HDT Connector Serial VID VFIX MODE VID Override table (VDD)
B 19 +1.5VSUS B
18 SVC SVD Output Voltage
17
CPU_LDT_RST_HTPA# 16 +1.5V 0 0 1.1V
CPU_DBREQ# 15
CPU_DBRDY 14 R203 1K/F_4 +1.5VSUS
0 1 1.0V
CPU_TCK 13 R181 R182 R204 1K/F_4
CPU_TMS 12 +1.5V 1 0 0.9V
CPU_TDI 11 SI Change HDT connector fo FFC type *1K/F_4 *1K/F_4
CPU_TRST# 10 CPU_SVC_R R188 *0_4/S CPU_SVC 1 1 0.8V
9 CPU_SVC 36
CPU_TDO CPU_SVD_R R189 *0_4/S CPU_SVD
8 CPU_SVD 36
CPU_PWRGD R191 *0_4/S CPU_PWRGD_SVID_REG
7 CPU_PWRGD_SVID_REG 36
CPUTEST12 R47 1K/F_4
6 CPUTEST19 R104 1K/F_4
5 CPUTEST18 R106 1K/F_4
4 R198 *220_4 CPUTEST20 R311 1K/F_4
3 R197 *220_4 CPUTEST21 R53 1K/F_4
2 R199 *220_4 CPUTEST22 R52 1K/F_4
1 CPUTEST24 R49 1K/F_4
HDT CONN
88511-2001-20p-l
+3V R224 10K/F_4 R187 10K/F_4
Can remove on MP +1.5VSUS +1.5VSUS
+1.5VSUS R225 300_4 +1.5VSUS R373 1K/F_4
2
Q23
A C718 MMBT3904 A
0.1U/10V_4 CPU_THERMTRIP_L# 1 3
5 CPU_THERMTRIP_L# CPU_THERMTRIP# 13
U30 CPU_PROCHOT_L# R209 *0_4/S
5
2
TC7SH08FU Q26
2 CPU_LDT_RST#
CPU_LDT_RST_HTPA# 4
1
32 CPU_PROCHOT#
R219 *0_4/S 1 3
MMBT3904
CPU_PROCHOT_R#
CPU_PROCHOT_R# 12 PROJECT : R22
Quanta Computer Inc.
3
EC new option Size Document Number Rev
Custom 1A
S1G4 HT,CTL I/F 1/3
NB5/RD2
Date: Wednesday, September 15, 2010Sheet 3 of 43
5 4 3 2 1
A B C D E
+1.5VSUS
R306
*0_4/S
PLACE THEM CLOSE TO
CPU WITHIN 1"
+0.9V
D10
C10
B10
AD10
U19B
VDDR2
VDDR3
VDDR5
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