Service Manuals, User Guides, Schematic Diagrams or docs for : Quanta Quanta_ZF1A
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ZF1A
AC/BATT
A DC/DC A
CONNECTOR PG 42 CPU VR CLOCKS
Dothan/Yonah +1.2V/+2.5V
+1.05V/+1.5V
+1.8V/+0.9V
+3V/+5V PG 37~41
PG 43 PG 3
(478 Micro-FCPGA)
BATT PG 4,5
CHARGER PG 42
4X133MHZ LCD Connector
+0.9V LVDS
+1.05V
+1.8VSUS
DVI +2.5V
400/533 MHZ DDR II Alviso M24P/M26P DVI
B
DDR-SODIMM1 PCI EXPRESS +3V B
PG 10,11 +1.5V
915PM DDRam(64/128) TVOUT
1257 PCBGA S-Video
400/533 MHZ DDR II +1.8VSUS PG 6,7,8,9 PG 12,13,14,15,16
+2.5V VGA
DDR-SODIMM2 CRT
PG 10,11 PG 16
DMI interface DOCKING
SATA
SATA-HDD PG 32
PG 33
IDE M5285 SATA 33MHz PCI
Parallel-HDDPG 32 +1.5V +1.05V
PG 32 +2.5V PCI
ICH6-M CARDBUS/1394
IDE +3V BUFFER LAN (10M/100M/1G) 1394(TSB43AB21)
Multi-Bay OZ711M3
+3VSUS 609 BGA
PG 31 MINI-PCI BCM5788M PG 20,21 PG 36
C +1.5VSUS Wireless LAN C
PG 22
Azalia PG 17,18,19 PG 28 PG 34
Smart 1394 PORT
Card
RJ45/Magnetics
PG 20 PG 20
Mini-Bluetooth USB
ALC880 NEW PG 23
MDC1.5 (USB bus) PCI-E OZ2710
(Codec) CARD CARDBUS
PG 24 3.3V LPC, 33MHz
& PG 29 CON.
PG 24
PG 29,30
PG 20
PG 24
+3V 3V_591 +5V 4 in 1
PC87383 SIO NSC97551 FAN 1 socket XD,MMC,SD,MS
PG 27 PG 20
Euphonik DSP Headphone/SPDIF 176 Pins LQFP
PG 35 PG 30 PG 25 PG 26
D D
PROJECT : ZF1A
Internal-MIC LINEIN/MICIN
PG 35 PG 30 +3/5V +5V +5V 3V_591 Quanta Computer Inc.
FIR Size Document Number Rev
Touchpad Keyboard FLASH BLOCK GIAGRAM
PG 30 A3A
PG 27 PG 26 PG 26 Date: Tuesday, August 02, 2005 Sheet 1 of 43
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
Check again
A
Change History A
Voltage Rails ON S0~S1 ON S3 ON S4 ON S5 Control signal
12VOUT X X X X 5/28
3V_591 X X X X 1.System DVI DET function move in EZ port , So,Del Q47,R557
5VPCU X X X X 2.Addition AND gate for DOCKING Power Good AND DockingIN Singal combine Circuit
3.Addition Power led circuit for system
+3V_S5 X X X X S5_ON 4.Change D34 AND D35 + -
3V_LAN X X X X 5.Addition LID Switch and LID connector
+1.5V_S5 X X X X S5_ON 6.Addition RC Delay for PCIE1.2V
+1.8VSUS X X SUSON 7.Change EC Three GPIO port same to ZL2
+3VSUS X X SUSD 5/31
+5VSUS X X SUSD 1.Change C145 PCB Footprint to 3528
SMDDR_VTERM DDR Termination voltage X X MAINON 2.Combine USB and bluetooth connector to 19pin connector 87212-1900
SMDDR_VREF X MAINON 3.Change PCBFootprint 88216-1200 to 88213-1200
VGA_PCIE_1.2V X MAINON 4.Change USB connector bypass C to 0805 10u
VCC_CORE Core voltage for Processor X VR_ON 5.Adujst 80pin connector 3 singal
6/1
1.Update power all circuit for GND name
+VCCP 1.05V rail for Processor I/O X MAINON 2.Addition OR to PRST
+1.5V X MAINON 3.Change IDE RST
+1.8V X MAIND 6/2
+2.5V X MAIND 1.Change ICH-6 USB Port
+3V X MAIND 2.Del CDR,CDL,CDGND Singal and DEL prevent CDR,CDL,CDGND noise circuit.
B +5V MAIND 6/4 B
1.U49,U50, Form 3VRUN change to +3V AND CHANGE MINPCI connector to PCI BUS,And addition PCI_SWRST # AND PCI_SWRST1#
+12V X MAINON 2.Change BT_POWER NAME
+3VRUN X PCI_Switch_Power_ON 3.Change VOIP AGND
+5VRUN X PCI_Switch_Power_ON
6/7
1.Change VOIP AGND TO AGND2 for Layout
External PCI Devices
C C
Device IDSEL# REQ#/GNT# Interrupts
CardBus+Smart Card AD25 1 PIRQC/B
Mini-PCI AD19 2 PIRQB/D
LAN AD22 0 PIRQA
1394 AD23 3 PIRQD
EC SM Bus1 address
Device
Smart Battery
THERMAL SENSOR
LIGHT SENER
VOIP FLASH ROM
D D
ICH6-M SM Bus address
Device PROJECT : ZF1A
SODIMM 1010 000X b
Quanta Computer Inc.
Clock Gen 1101 001x b
Size Document Number Rev
SYSTEM INFO A3A
Date: Tuesday, August 02, 2005 Sheet 2 of 43
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
VDD_CKG_CPU
L26
ACB2012L-120
1 2 VDD_CKG_CPU R115 2.2 VDDA_CKG
+3V
Close to Clock Gen.
1
1
1
1
1
C339 C346 C345 C358 C359
1
1
C679 C342 R128 1 2 49.9/F_4
10U/10V_8 .047U_4 .047U_4 .047U_4 .047U_4 R127 1 2 49.9/F_4
2
2
2
2
2
.047U_4 10U/10V_8
2
2
R126 1 2 49.9/F_4
R125 1 2 49.9/F_4
2 1 CG_XIN R129 12.1/F_4
C722 33P_4 R124 1 2 49.9/F_4 1 2 14M_SIO (25)
1
U50 R123 1 2 49.9/F_4
37
38
A A
Y4 R130 12.1/F_4
14.318MHZ/20PF 50 52 14M_REF 1 2
VDDA
VSSA
XTAL_IN REF 14M_ICH (18)
2
2 1 CG_XOUT 49 44 R_HCLK_CPU 4 3 RP42
XTAL_OUT CPU0 HCLK_CPU (4)
C682 33P_4 43 R_HCLK_CPU# 2 1
CPU0# HCLK_CPU# (4)
4P2R-S-33
CLK_EN#_C 10 41 R_HCLK_MCH 4 3 RP43
VTT_PWRGD#/PD CPU1 HCLK_MCH (6)
55 40 R_HCLK_MCH# 2 1
(18) STP_PCI# PCI/SRC_STOP# CPU1# HCLK_MCH# (6)
54 4P2R-S-33
(18,43) STP_CPU# CPU_STOP#
36 R_PCIE_VGA 4 3 RP39
CPU2_ITP/SRC5 CLK_PCIE_VGA (12)
SMbus address D2 35 R_PCIE_VGA# 2 1
CPU2#_ITP/SRC5# CLK_PCIE_VGA# (12)
4P2R-S-33
CGCLK_SMB 46 33 NEW_CLKREQ# CLKREQA# - SRC0, 2, SATA
SCLK *CLKREQA# NEW_CLKREQ# (24)
CGDAT_SMB 47 32 EZ_CLKREQ#
SDATA *CLKREQB# EZ_CLKREQ# (33) CLKREQB# - SRC1, 3, 4
(18) CLK48_USB
R154 1 2 33_4 SELPSB0_CLK 12 FSA/USB_48 SRC4 31 R_PCIE_EZ2 4 3 RP40 CLK_PCIE_EZ2 (33) S/W programable for
SELPSB1_CLK 16 30 R_PCIE_EZ2# 2 1
(5,7) SELPSB1_CLK
SELPSB2_CLK 53
FSB/TEST_MODE SRC4# 4P2R-S-33
CLK_PCIE_EZ2# (33) effected clock pairs
R411 (5,7) SELPSB2_CLK FSC/TEST_SEL
SATACLK 26 R_PCIE_SATA 2 1 4P2R-S-33 CLK_PCIE_SATA (17)
VDD_CKGREF 48 27 R_PCIE_SATA# 4 3
VDD_REF SATACLK# RP54 CLK_PCIE_SATA# (17)
1/F_4 1 24 R_MCH_3GPLL 2 1 RP53
VDD_PCI_1 SRC3 CLK_MCH_3GPLL (7)
+3V 1 2 CLKVDD 7 25 R_MCH_3GPLL# 4 3
VDD_PCI_2 SRC3# CLK_MCH_3GPLL# (7)
CK-410M 4P2R-S-33
1
1
1
1
L28 ACB2012L-120 C360 C745 C744 C343 VDD_CKG_CPU VDD_CKG_CPU 42 VDD_CPU SRC2 22 R_PCIE_ICH 2 1 4P2R-S-33 CLK_PCIE_ICH (18)
R145 21 23 R_PCIE_ICH# 4 3
VDD_SRC0 SRC2# RP52 CLK_PCIE_ICH# (18)
2.2 10U/10V_8 .047U_4 .047U_4 .047U_4 28
2
2
2
2
VDD_SRC1 R_PCIE_EZ1
34 VDD_SRC2 SRC1 19 2 1 RP51 CLK_PCIE_EZ1 (33)
20 R_PCIE_EZ1# 4 3
SRC1# CLK_PCIE_EZ1# (33)
VDD_CKG_48 11 4P2R-S-33
VDD_48
R380 475/F_4
LCDCLK_SST/SRC0 17 R_PCIE_NEWC 2 1 4P2R-S-33 CLK_PCIE_NEWC (24)
1
1
C361 C746 Iref=5mA, IREF 39 18 R_PCIE_NEWC# 4 3
Ioh=4*Iref IREF LCDCLK_SSC/SRC0# RP50 CLK_PCIE_NEWC# (24)
10U/10V_8 .047U_4 5 R_PCLK_LAN
2
2
*Internal Pull-UP Resistor PCI5
PCI4 4
4P2R-S-33 3 R_PCLK_MINI R158 1 2 33_4
GND_PCI_1
GND_PCI_2
PCI3 PCLK_MINI (28)
GND_SRC
GND_CPU
GND_REF
1 2 4 3 R_DOT96 14 56 R_PCLK_SIO R133 1 2 33_4
(7) DREFSSCLK DOT96 PCI2 PCLK_SIO (25)
GND_48
B 3 4 2 1 R_DOT96# 15 9 R_PCLK_591 R155 1 2 33_4 B
(7) DREFSSCLK# DOT96# *PCIF1/LCD_EN# PCLK_591 (26)
8 R_PCLK_ICH R424 33_4
RP49 PCIF0/ITP_EN PCLK_ICH (17)
RP55
4P2R-S-0
R412 Pin 8 Strapping
(7) DOT96#
13
51
2
6
29
45
U65 ICS954217 10K_4
(7) DOT96 250mA ( MAX. ) High : Pin35/36 = Host Clock
ICS9112AM-16T
R_PCLK_LAN 1 REF CLKOUT 8 R705 33_4
PCLK_LAN (22) Low : Pin35/36 = SRC Clock
R_PCLK_PCM R706 33_4
PCLK_PCM (20) +3V
2 7 R_PCLK_1394 R708 33_4
CLK2 CLK4 PCLK_1394 (36)
3 CLK1 VDD 6 CLKVDD
NEW_CLKREQ# R606 1K_4
4 5 EZ_CLKREQ# R607 1K_4
GND CLK3
+VCCP +VCCP +3V DOT96 R153 1 2 49.9/F_4
Resistor Stuff Table
DOT96# R152 1 2 49.9/F_4
CLK_MCH_3GPLL R122 1 2 49.9/F_4
RA RB RC RD R132 R423 R164 CLK_MCH_3GPLL# R121 1 2 49.9/F_4
RA *1K_4 RC *1K_4 10K_4
Dothan A 400 V X X V CLK_PCIE_SATA R160 1 2 49.9/F_4
CLK_PCIE_SATA# R161 1 2 49.9/F_4
Dothan A 533 X V X V SELPSB2_CLK SELPSB1_CLK SELPSB0_CLK
CLK_PCIE_ICH R149 1 2 49.9/F_4
Dothan B X X X X CLK_PCIE_ICH# R148 1 2 49.9/F_4
R131 R422
RB 1K_4 RD 1K_4 CLK_PCIE_EZ2 R147 1 2 49.9/F_4
+3V CLK_PCIE_EZ2# R146 1 2 49.9/F_4
CLK_PCIE_NEWC R163 1 2 49.9/F_4
CLK_PCIE_NEWC# R162 1 2 49.9/F_4
2
4
RP41 Clock Gen. Frequency Selection Table CLK_PCIE_EZ1 R151 1 2 49.9/F_4
CLK_PCIE_EZ1# R150 1 2 49.9/F_4
4P2R-S-10K
C C
FSC FSB FSA CPU SRC PCI Close to Clock Gen.
2
1
3
Q29 1 0 1 100 100 33 DOTHAN BSEL Output Value
3 1 CGDAT_SMB
(18,24,33) PDAT_SMB CGDAT_SMB (10)
RHU002N06
0 0 1 133 100 33
0 1 1 166 100 33 FSB DOTHAN A-Step DOTHAN B-Step
+3V Frequency BSEL1 BSEL0 BSEL1 BSEL0
0 1 0 200 100 33
0 0 0 266 100 33
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