Service Manuals, User Guides, Schematic Diagrams or docs for : Quanta Quanta_ZI9
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5 4 3 2 1
5VPCU
5V --- 3.0Amps 3V_591 Block Diagram HOST 100MHz
PCI-E 100MHz
3V --- 6.0Amps 3V_S5 CLOCK GEN
CK505
3VSUS VGA 96MHz
ICS9LP208
D 5VSUS D
USB 48MHz
+3V Based on Optimized
Dothan Core PCI 33MHz
+5V
0.6mm pitch 14*19mm
+10V REF 14MHz
+1.8VSUS
1.8V --- 2.5Amps
+1.8V
0.9V --- 1.0Amps HOST BUS
2.5V --- 0.5Amps +0.9VSUS 400MHz
+0.9V S-Video Docking
LVDS
+2.5V LCD Little River GMCH
0.6mm pitch 22*22mm PCI-E
1.5V_S5 DDR2 SDRAM
4 X 16 MINI Card HDMI
1.5V --- 2.8Amps +1.5V Speaker
1.05V --- 4.5Amps SDVO
DDR2 400MHz SDVO to HDMI MIC
AGP_VCC (+1.5V)
C module USB Client C
1.2VCCT TV-OUT
DMI I/F SPDIF-O USB TO CRT
VTT
HP
Azalia OUT
AUDIO CODEC AMP
VCC_CORE
HDD PATA ICH7-U
0.65mm pitch 15*15mm
Vcore ( IMVP-4 )
Vid : 0.8 ~ 1.05
INT INT
Max : 8Amps SYSTEM
USB0 USB 2.0 MIC SPK
ext USB*1
MIC & LINEOUT
BATTERY
CHARGER USB1
Touchscreen PCI ROUTING TABLE IDSEL INTERRUPT DEVICE
REQ3# / GNT3# AD22 INTE# Richo Card-Reader
5 IN 1
PCI BUS Winbond
USB2 MMC/SD/MS/MS PRO
B USB TV CardReader B
Power State Table LPC
Power Control Power USB3
Name Signal State Bluetooth
SDIO
+3VPCU N/A ALWAYS
+3V_S5 S5_ON S0 - S5 Winbomd KBC Winbond SIO
USB4.5
+3VSUS SUSON S0 - S3 Docking
+3V MAINON S0 X2
+5VPCU N/A ALWAYS
+5V_S5 S5_ON S0 - S5 USB6
+5VSUS SUSON S0 - S3
CCD INT KB BIOS
Serial Port
+5V MAINON S0
+1.8VSUS SUSON S0 - S3
Finger-print USB7
SMDDR_VTERM MAINON S0
or
A +1.05V MAINON S0 MINI Card A
+1.5V MAINON S0
+2.5V MAINON S0 QUANTA COMPUTER
+VCC_CORE VRON S0 HW Engineer :
Title
Size :
Block Diagram
Document Number : Rev :
X ZI9 --- Block Diagram A1A
Date : Monday, August 21, 2006 Sheet 1 of 22
5 4 3 2 1
5 4 3 2 1
U1
ICS9LP208
VRM_CLKEN# 10 44 HCLK_CPU_R 1 2 RP1 HCLK_CPU
[20] VRM_CLKEN# PM_STPCPU# VTT_PWRGD//PD CPUCLKT0 HCLK_CPU# HCLK_CPU [3]
54 43 HCLK_CPU_R# 3 4 33_4P2R_4
[10] PM_STPCPU# PM_STPPCI# CPU_STOP CPUCLKC0 HCLK_CPU# [3]
[10] PM_STPPCI# 55 PCI//PCIE_STOP
41 HCLK_MCH_R 1 2 RP2 HCLK_MCH
CPUCLKT1 HCLK_MCH# HCLK_MCH [5]
CLKREQB# 32 40 HCLK_MCH_R# 3 4 33_4P2R_4
D MINI_CLKREQ# CLKREQB# CPUCLKC1 HCLK_MCH# [5] D
[5,16] MINI_CLKREQ# 9 CLKREQA#
36 HCLK_ITP
CGDAT_SMB CPUCLKT2/PCIEXT4 HCLK_ITP# HCLK_ITP [13]
47 SDATA CPUCLKC2/PCIEXC4 35 HCLK_ITP# [13]
CGCLK_SMB 46 SCLK
Enable clock output for XDP/ITP
R1 4.75K/F_4 39 31 PECLK_XDP
VREF PCIEXT4 PECLK_XDP# PECLK_XDP [13]
PCIEXC4 30 PECLK_XDP# [13]
L1 HB-1T2012-121JT VDD_SRC_CPU 42
+3V VDDCPU PECLK_MINI
21 26 PECLK_MINI_R 3 4 RP3
VDDPCIE1 SATACLKT PECLK_MINI# PECLK_MINI [16]
28 27 PECLK_MINI_R# 1 2 33_4P2R_4
VDDPCIE2 SATACLKC PECLK_MINI# [16]
34 VDDPCIE3
C1 C2 C3 C4 C5 22 PECLK_ICH_R 3 4 RP4 PECLK_ICH
PCIEXT2 PECLK_ICH# PECLK_ICH [10]
10U/10V_8 .1U_4 .1U_4 .1U_4 .1U_4 37 23 PECLK_ICH_R# 1 2 33_4P2R_4
VDDA PCIEXC2 PECLK_ICH# [10]
R2 2.2_6 VDDA_CK 19 PECLK_MCH_R 3 4 RP5 PECLK_MCH
PCIEXT1 PECLK_MCH# PECLK_MCH [5]
1 20 PECLK_MCH_R# 1 2 33_4P2R_4
VDDPCI1 PCIEXC1 PECLK_MCH# [5]
7 VDDPCI2
17 DREFCLK_SS_R 3 4 RP6 DREFCLK_SS
LCDCLK_SST//SRCCLKT0 DREFCLK_SS# DREFCLK_SS [5]
C6 C7 18 DREFCLK_SS_R# 1 2 33_4P2R_4
LCDCLK_SSC//SRCCLKC0 DREFCLK_SS# [5]
10U/10V_8 .1U_4 11 VDD48 DREFCLK_R DREFCLK
DOTT_96M 14 3 4 RP7 DREFCLK [5]
L2 HB-1T2012-121JT VDD_PCI 48 15 DREFCLK_R# 1 2 33_4P2R_4 DREFCLK#
+3V VDDREF DOTC_96M DREFCLK# [5]
C C
C8 C9 C10 5 SELPCIE0 R3 *33_4 PCLK_DEBUG
PCICLK5 PCLK_5IN1 PCLK_DEBUG [13] PCLK_5IN1
10U/10V_8 .1U_4 .1U_4 4 PCLK_5IN1_R R4 33_4 C11 *10P_4
PCICLK4 PCLK_EC PCLK_5IN1 [14]
3 PCLK_EC_R R5 33_4
VDD_48M PCICLK3 PCLK_EC [15] PCLK_EC
R6 2.2_6 56 PCLK_SIO_R R7 33_4 PCLK_SIO C12 *10P_4
PCICLK2 PCLK_SIO [13]
2 GND1
6 8 PCLK_ICH_R R8 33_4 PCLK_ICH PCLK_SIO C13 *10P_4
GND2 ITP_EN//PCICLK_F0 PCLK_ICH [10]
13 GND3
C15 C16 16 PCLK_ICH C14 *10P_4
10U/10V_8 .1U_4 GND4
24 GND5
25 52 14M_REF0 R9 33_4 14M_ICH 14M_ICH C17 *10P_4
VDDREF_CK GND6 REF0//SELSRC_LCDCLK# FSB_SELA 14M_SIO 14M_ICH [10]
R10 1_6 29 53 R11 33_4
GND7 REF1/FSA 14M_SIO [13] 48M_USB
33 C20 *10P_4
GND8
45 GND9
51 12 R12 33_4 48M_USB
GND19 USB_48M 48M_USB [10]
C18 C19
10U/10V_8 .1U_4 38 GNDA
X1
X2
50
49
Y1
14.318MHz
+3V
B B
MINI_CLKREQ# R13 10K_4
PCLK_ICH_R R353 *10K_4
C21 C22
33P_4 33P_4 1 : ITP CLK R18 *10K_4
Stealey BSEL[1:0]=01 ---> 400 MHz
CK505 BSEL[2:0]=101 ---> 400 MHz 0 : SRC CLK R20 10K_4
ICS9LP208 FSA=1 ---> 400 MHz CLKREQB# R15 *10K_4
FSA=0 ---> 533 MHz 14M_REF0 R16 10K_4
+1.05V +1.05V
R21 R22
1K_4 1K_4
3 1 CGCLK_SMB
FSB_SELB [10] PCLK_SMB
R24 *0_4 R25 0_4 FSB_SELA R26 0_4
[3] CPU_BSEL0 [3] CPU_BSEL1
A R29 1K_4 R30 1K_4 R14 10K_4 A
[5] MCH_BSEL0 [5] MCH_BSEL1
Q1
2N7002E QUANTA COMPUTER
2
+3V
2
R32 R33
R17 10K_4 HW Engineer :
*1K_4 *0_4 3 1 CGDAT_SMB Title
[10] PDAT_SMB
Size :
Clock Generator - ICS9LP208
Document Number : Rev :
Q2
2N7002E X ZI9 --- Clock Generator A1A
Date : Monday, August 21, 2006 Sheet 2 of 22
5 4 3 2 1
5 4 3 2 1
U2A
Stealey +3V
HA#3 AB2 D22 HD#0
[5] HA#3 HA#4 A3# D0# HD#1
[5] HA#4 AD4 A4# D1# H28
HA#5 AB6 A23 HD#2
[5]
[5]
HA#5
HA#6
HA#6
HA#7
Y4
A5#
A6#
D2#
D3# E25 HD#3
HD#4
SMBUS Address : 98
[5] HA#7 AJ1 A7# D4# D26
HA#8 AK2 F28 HD#5
[5] HA#8 HA#9 A8# D5# HD#6
AB4 D24 U3 R35 R36
[5] HA#9 HA#10 A9# D6# HD#7
AH2 E23 G784 10K_4 2.2K_4
[5] HA#10 HA#11 A10# D7# HD#8
AH4 B22 MBDATA 7 4 FAN_OVT#
[5] HA#11 HA#12 A11# D8# HD#9 [15,21] MBDATA SDAT OVT FAN_OVT# [16]
AL1 B26 MBCLK 8
D [5] HA#12 HA#13 A12# D9# [15,21] MBCLK SCLK D
AG1 D30 HD#10 6 CPU_THMALT#
[5] HA#13 HA#14 A13# D10# ALERT CPU_THMALT# [15]
AF4 G31 HD#11 R37 47_6 3V_THM 1
[5] HA#14 HA#15 A14# D11# HD#12 +3V VCC
AK4 B28 2 H_THERMDA
[5] HA#15 HA#16 A15# D12# HD#13 DXP
[5] HA#16 AM2 A16# D13# G27
HADSTB0# HD#14
[5] HADSTB0# AF2 ADSTB0# D14# F30
HD#15 C23
5 GND DXN 3 Width : 10mil
A27 HD#[15..0] [5]
[5] HREQ#0
HREQ#0 AC1
D15#
E31 HDINV#0
HDINV#0 [5]
.1U_4 C24 Length < 500mil
HREQ#1 REQ0# DINV0# HDSTBN#0 2200P_4 H_THERMDC
[5] HREQ#1 AA1 REQ1# DSTBN0# A25 HDSTBN#0 [5]
HREQ#2 AE1 B24 HDSTBP#0
[5] HREQ#2 HREQ#3 REQ2# DSTBP0# HDSTBP#0 [5]
[5] HREQ#3 Y2 REQ3#
HREQ#4 AD2 L31 HD#16
[5] HREQ#4 REQ4# D16#
J31 HD#17
HA#17 D17# HD#18
[5] HA#17 AY4 A17# D18# T28
HA#18 AP6 U31 HD#19 +1.05V
[5] HA#18 HA#19 A18# D19# HD#20
[5] HA#19 AV6 A19# D20# M30
HA#20 AR1 H30 HD#21
[5] HA#20 A20# D21#
3
HA#21 AU1 K30 HD#22
[5] HA#21 HA#22 A21# D22# HD#23
[5] HA#22 AW1 A22# D23# R27
HA#23 AP2 V30 HD#24
[5] HA#23 HA#24 A23# D24#
AM6 N31 HD#25 2
[5] HA#24 HA#25 A24# D25# HD#26 [5,10,20] VRM_PWRGD
[5] HA#25 AT6 A25# D26# V28
HA#26 AV2 Y30 HD#27
[5] HA#26 HA#27 A26# D27#
AP4 W27 HD#28 Q3
[5] HA#27 HA#28 A27# D28# HD#29 +1.05V
AV4 P28 2N7002E
[5] HA#28 HA#29 A28# D29# HD#30
1
[5] HA#29 AY2 A29# D30# W31
HA#30 AN1 U27 HD#31
C [5] HA#30 A30# D31# HDINV#1 HD#[31..16] [5] C
HA#31 AT4 T30
[5] HA#31 HADSTB1# A31# DINV1# HDSTBN#1 HDINV#1 [5]
[5] HADSTB1# AT2 ADSTB1# DSTBN1# P30 HDSTBN#1 [5]
R31 HDSTBP#1
DSTBP1# HDSTBP#1 [5]
R38 R341
H_ADS# W1 AF28 HD#32 R39 1K_4 10K_4
[5] H_ADS# ADS# D32#
2
H_BNR# T4 AG27 HD#33 56_4
[5] H_BNR# H_BPRI# BNR# D33# HD#34
[5] H_BPRI# M2 BPRI# D34# AC27
H_DEFER# U1 AJ31 HD#35 R_THERMTRIP# R40 33_4 RR_THERMTRIP# 1 3
[5] H_DEFER# H_DRDY# DEFER# D35# HD#36 SYS_SHT# [17]
T2 AK30 Q4
[5] H_DRDY# H_DBSY# DRDY# D36#
T6 AC31 HD#37 MMBT3904
[5] H_DBSY# H_BREQ#0 DBSY# D37#
V4 AA31 HD#38
[5] H_BREQ#0 BR0# D38# HD#39
H_LOCK# L1 AD30
[5] H_LOCK# H_CPURST# LOCK# D39# HD#40
[5,13] H_CPURST# D14 RESET# D40# AK28
H_RS#0 M4 AB30 HD#41
[5] H_RS#0 H_RS#1 RS0# D41# HD#42
[5] H_RS#1 N1 RS1# D42# AE27
H_RS#2 P2 AD28 HD#43
[5] H_RS#2 H_TRDY# RS2# D43# HD#44 +3V +3V
[5] H_TRDY# V2 TRDY# D44# AF30
H_HIT# P4 AM30 HD#45
[5] H_HIT# H_HITM# HIT# D45# HD#46
[5] H_HITM# R1 HITM# D46# AL31
AH28 HD#47
H_IERR# D47# HDINV#2 HD#[47..32] [5]
B8 IERR# DINV2# AE31 HDINV#2 [5]
H_FERR# F4 AG31 HDSTBN#2
[10] H_FERR# H_IGNNE# FERR# DSTBN2# HDSTBP#2 HDSTBN#2 [5]
D10 AH30 R41 R42
[10] H_IGNNE# H_INIT# IGNNE# DSTBP2# HDSTBP#2 [5]
D8 1K_4 330_4
[10] H_INIT# H_SMI# INIT# HD#48 THERM_ALERT# [10]
[10] H_SMI# A5 SMI# D48# AP30
3
B H_INTR H6 AU31 HD#49 B
[10] H_INTR H_NMI INTR D49# HD#50
[10] H_NMI E1 NMI D50# AN31 2
R43 0_4 H_STPCLK_R# B6 BA27 HD#51
[10] H_STPCLK# STPCLK# D51#
3
H_A20M# E9 AP28 HD#52 Q5
[10] H_A20M# A20M# D52# HD#53 H_PROCHOT_R# +1.05V
R342 1K_4 MMBT3904
1
D53# AR31 2
H_PWRGD F6 AT28 HD#54
[10,13] H_PWRGD H_CPUSLP# PWRGOOD D54# HD#55
A7 AR27 Q6
[5,10] H_CPUSLP# PSI# SLP# D55# HD#56 MMBT3904
1
T20 AY8 PSI# D56# AN27
AT30 HD#57 H_PWRGD R45 *200/F_6
H_DPSLP# D57# HD#58
[10] H_DPSLP# A9 DPSLP# D58# BC27
H_DPWR# E21 AW27 HD#59 H_IERR# R46 56_4
[5] H_DPWR# DPWR# D59# HD#60
D60# AU27
XDP_BPM#0 B10 AV28 HD#61 H_PROCHOT_R# R47 75_4
[13] XDP_BPM#0 BPM0# D61# HD#62
XDP_BPM#1 A11 AY28
[13] XDP_BPM#1 BPM1# D62# HD#63 XDP_TMS
XDP_BPM#2 D12 AV30 R48 54.9/F_4
[13] XDP_BPM#2 BPM2# D63# HDINV#3 HD#[63..48] [5]
XDP_BPM#3 E13 BB28
[13] XDP_BPM#3 BPM3# DINV3# HDSTBN#3 HDINV#3 [5] XDP_TDI
AY30 R49 54.9/F_4
+1.05V DSTBN3# HDSTBN#3 [5]
AW31 HDSTBP#3
XDP_TMS DSTBP3# HDSTBP#3 [5]
[13] XDP_TMS E15 TMS T6
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