Service Manuals, User Guides, Schematic Diagrams or docs for : Samsung DVD DVD HR720 DVD-HR720_part1
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8. Block Diagram
8-1 All Block Diagram - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 8-2
8-2 DIC1 (DMN8602) Block Diagram - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 8-3
8-3 AIC1 (PCM1742) Block Diagram- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 8-4
8-4 AIC9 (PCM1802) Block Diagram- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 8-5
8-5 PIC1 (TSB4AB1) Block Diagram- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 8-6
8-6 TIC1 (TVP5146) Block Diagram - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 8-7
Samsung Electronics This Document can not be used without Samsung's authorization. 8-1
Block Diagram
8-1 All Block Diagram
HDD80GB
4MB FLASH 64MB DDR-SDRAM
AM290L323GB K4H561638F-TCB3 AV OUT (L/R)
OSD_SEL
(2Mx 16bit) (16Mx 16bitx2wa)
OSD
NM1501
CVBS S-Video 1
Audio
NM1623 Video 1 DAC NOM1647
L/R
SCART1 (TV)
MPEG-2 Component
A/V CODEC Front Micom
CVBS NM1647 SCART1 (TV)
mux
MM1501 BU4052 SCART2 (EXT)
Audio
Front Micom ADC
Tuner RF Tuner
RGB SCART2 (EXT) mux
AVI (L/R)
EXT2
Video BD3824
Decoder RF RF Tuner EXT3
NJM 2267 EXT1 Front AV2 (L/R)
AV3
(6dB AMP) VPS/Sync OSD
CVBS/Y Detector
mux
(A/I)
AV3 (L/R)
AV1 (CVBS) RGB
V/C
AV2 (CVBS) CVBS
8-2 This Document can not be used without Samsung's authorization. Samsung Electronics
Block Diagram
8-2 DIC1 (DMN8602) Block Diagram
Samsung Electronics This Document can not be used without Samsung's authorization. 8-3
Block Diagram
8-3 AIC1 (PCM1742) Block Diagram
8-4 This Document can not be used without Samsung's authorization. Samsung Electronics
Block Diagram
8-4 AIC9 (PCM1802) Block Diagram
Samsung Electronics This Document can not be used without Samsung's authorization. 8-5
Block Diagram
8-5 PIC1 (TSB4AB1) Block Diagram
8-6 This Document can not be used without Samsung's authorization. Samsung Electronics
Block Diagram
8-6 TIC1 (TVP5146) Block Diagram
Copy VBI
CVBS/Y/G
Protection Data
Detector Slicer
Analog Front End
VI_1_A Composite and S-Video Processor
CVBS/ VI_1_B ADC1
Pb/B/C Y/C
VI_1_C CVBS/Y Y Luma
Separation
Processing YCbCr
5-line
VI_2_A C C Chroma Y[9:0]
CVBS/ Adaptive
VI_2_B ADC2 Processing
Y/G Comb C[9:0]
VI_2_C Output
M
Formatter
U FSS
VI_3_A X
CVBS/ Y/G Component
VI_3_B ADC3
Pr/R/C Processor
VI_3_C Pb/B YCbCr
Color
Gain/Offset Space
Pr/R Conversion
CVBS/Y VI_4_A ADC4
GPIO
Sampling
Clock Timing Processor
Host
with Sync Detector
Interface
XTAL1
XTAL2
VS/VBLK
AVID
GLCO
DG
DR
DB
FSO
SCL
SDA
HS/CS
PWDN
DATACLK
FID
RESETB
Samsung Electronics This Document can not be used without Samsung's authorization. 8-7
Block Diagram
MEMO
8-8 This Document can not be used without Samsung's authorization. Samsung Electronics
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