Service Manuals, User Guides, Schematic Diagrams or docs for : Samsung Laptop MONACO NP_G15 MONACO-R NP_G15
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4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
D TABLE OF CONTENTS D
1. COVER PAGE 36. LAN CONTROLLER
2. BLOCK DIAGRAM 37. USB PORTS
3. POWER DIAGRAM 38. KBD / TPAD / LED / SW
39. MXM CONN
MONACO-R 4. CLOCK DIAGRAM
5. RESET DIAGRAM 40. 3.3V_ALW / 5V_ALW POWER
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6. BOARD INFORMATION 41. 1.2V / VCCP POWER
7. CLOCK GENERATOR 42. DDR2 POWER
43. CPU POWER
8. CPU (1/3)
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44. 12V / MXM 1.8V POWER
9. CPU (2/3) 45. SWITCHED POWER
CPU :MEROM 10. CPU (3/3) 46. POWER STRAPS
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11. THERMAL SENSOR / FAN CONTROL 47. TEST POINTS
Chip Set :ATI RS600ME & SB600 12. NORTH BRIDGE (1/5)
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C C
13. NORTH BRIDGE (2/5)
Remarks :DESKNOTE 14. NORTH BRIDGE (3/5)
15. NORTH BRIDGE (4/5)
16. NORTH BRIDGE (5/5)
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17. DDR2 - SODIMM
18. DDR2 - TERMINATION
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19. SOUTH BRIDGE (1/4)
Model Name : MONACO-R 20. SOUTH BRIDGE (2/4)
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21. SOUTH BRIDGE (3/4)
PBA Name : MAIN 22. SOUTH BRIDGE (4/4)
23. STRAPS OPTION
PCB Code : BA41-00720A 24. FWH
25. CRT PORT
Dev. Step : PR
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26. LCD / TV-OUT
B 27. MINI PCI A B
Revision : 1.1 28. MINI PCI B
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29. AUDIO CODEC
T.R. Date : 2007.01.03 30. AUDIO AMP
C
31. AUDIO / MDC CONN
32. HDD / ODD / DMB
33. MICOM
34. 5-IN-1 CONTROLLER (1/2)
DRAW CHECK APPROVAL 35. 5-IN-1 CONTROLLER (1/2)
A A
SON,C.W LEE,S.P LIM,J.G SAMSUNG
ELECTRONICS
4 3 2 1
4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG. FAN CPU
Mobile Processor VRM
PG 11 IMVP-6
CPU
Merom - 2M/4M
PG 43
D Thermal (667MHz) DDR II Switche PWR
D
Sensor
PG 11 L2 Cache : 2/4 MB
VRM
PG 45
PG 9,10,11 478pin PG 42
LCD FSB
667 MT/S
40P
PG 26
DDR II 800/667/533/400 DDR II PG 17
LVDS 2ch SODIMM 0
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CRT
Internal Graphics RS600ME
DDR II 800/667/533/400 DDR II PG 17
CRT
SODIMM 1
1021 FCBGA
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PG 25
PG 26 TV ANT
PG 12 ~ 16
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SVHS / Composit
Wireless LAN
ALINK EXPRESS II
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C Clocking C
Mini PCI CONN.
CK-410M PG 27
64 PIN
PG 7 33MHz, 3.3V PCI
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USB 0,2,3,4,5 Mini PCI CONN.
PG 36 USB 0,2,3,4,5 ANT PG 28
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PG 38
AUDIO SB600 33MHz, 3.3V PCI
Audio 549 BGA
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AZALIA AZALIA Primary
AMP
Codec
ALC262 12P
PG 30 PG 29
AZALIA
AZALIA Secondary
RJ11 MDC PG 19 ~ 23 PCI LAN
RTL8100CL RJ45
HP Modem
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PG 36
MIC-IN PG 31 PG 37
PG 31
B B
o
SPI
2P 2P
PG 24
SATA
C
PG 32 HDD
PG 38
SPKR R
Touch
PATA 3.3V LPC, 33MHz
MICOM PAD
PG 32 ODD Hitachi H8S
H8S-2110B
SPKR L KBD
PG 33 PG 38
A A
SAMSUNG
ELECTRONICS
4 3 2 1
4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
Power Diagram
KBC3_RST* KBC3_SUSPWRON KBC3_PWRON KBC3_VRON VCCP3_PWRGD
D D
AC Adapter
VCCP VCC_CORE
P12V
VDC
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P1.8V_AUX P0.9V
SODIMM (DDR II) DDR II-Termination
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DDR II for PEG (TBD)
C
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MICOM_P3V
P5V_ALW
MICOM SB
C
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P5V
P1.2V
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P3.3V_ALW P3.3V
S f
P1.2V_ALW
P2.5V
P12V_ALW
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P1.8V
B B
State
Full On
S3
S4
S5
Rail
+V*Always +V*AUX
ON
ON
ON
ON
ON
ON
OFF
OFF
+V
ON
OFF
OFF
OFF
SUSPWR PWRON
H
H
L
L
H
L
L
L
VRON
H
L
L
L Co P1.5V
S5 / S4 S3 S0
A A
SAMSUNG
ELECTRONICS
4 3 2 1
4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
CLK0_HCLK0
D D
CLK0_HCLK0* MEROM
CLK0_HCLK1
CLK0_HCLK1*
CLK1_PCIEICH RS600ME
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CLK1_PCIEICH*
CLK1_PCIEGFX
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CLK1_PCIEGFX*
CLK3_NB14M
C
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CLK1_PCIERCLK
CLK1_PCIERCLK*
33MHZ
33MHZ
MINI PCI A
MINI PCI B
C
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CLOCK GENERATOR CLK3_USB48
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33MHZ
LAN 25MHZ
CLK3_ICH14
S f
33MHZ
SB600 FWH
33MHZ
MICOM 10MHZ
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33MHZ
B 5-IN-1 B
o
25MHz
AC_BITCLK
AUDIO
C 14.318 MHz
A A
SAMSUNG
ELECTRONICS
4 3 2 1
4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
23
MINIPCI A PCIRST_MINIA*
PCIRST_MINIB*
22 HTMCP_PWRGD
D PCIRST_DEV*
SB 24 HTMCP_RST* D
23
MINIPCI B
PCIRST_IDE*
PLT3_RST*
23 11 10
LAN / 5-IN-1
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KBC3_PWRBTN*
KBC3_RSMRST*
MCP3_SLPS3*
MCP3_SLPS5*
23
ODD
FWH
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21
9 6
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C VDC 1 C
KBC3_SUSPWR* 7
MICOM_P3V 2 MAX8734 6
KBC3_PWRON 12 MICOM KBC3_PWRSW* NB
P3.3V_ALW 4
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P5V_ALW 4 PAGE 48
PAGE 8
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KBC3_RST*
MCP3_PWRGD
15 12
CPU1_PWRGD
CPU1_RESET*
3
S f
MICOM
5 P1.5V_ALW RESET
MIC5219 HT_PWRGD
LOGIC
20 14
25 26
13 P1.5V
MIC5219
KBC3_HTPON
18 VCC_NB
5 ISL6227 13
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P1.2V_ALW
12
B
MIC5219
8 P1.8V_AUX
KBC3_PWRON P1.2V
CPU B
MAX8632
13
KBC3_VRON
o
8 P0.9V_AUX
P1.2V_HT
U600 19
PAGE 12
VRM3_CPU_PWRGD 17 16
13 CPU_CORE
C
P12V
LM2941 PAGE 45
13 P5V
SI4435
13 P3.3V
FDS6680
13 P2.5V
SC3381 13 P1.8V
A A
13 P1.5V
MIC5219 SAMSUNG
ELECTRONICS
4 3 2 1
4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
D
SCHEMATIC ANNOTATIONS AND BOARD INFORMATION D
PCI Devices Crystal / Oscillator
Devices IDSEL# REQ/GNT# Interrupts TYPE FREQUENCY DEVICE USAGE
MINIPCI A AD21 0 A,B
AD22 1 Crystal 25MHz MCP51 MCP51 REF CLOCK
MINIPCI B C,D Crystal 32.768KHz MCP51 Real Time Clock
LAN AD23 2 D
5-IN-1 AD24 3 B Crystal 10MHz MICOM H8S-2110B
Crystal 27MHz C51MV TV OUT
USB AD30(internal)
Crystal 25MHz LAN RTL8110CL
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Hub to PCI AD31(internal)
LPC bridge/IDE/AC97/SMBUS AD31(internal)
Internal MAC AD31(internal)
Voltage Rails
VDC
CPU_CORE
Primary DC system power supply (7 to 21V)
Core voltage for AMD SEMPRON (1.308~1.068V)
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C VCC_NB SEMPRON Processor Hyper Trasnport (1.2V) C
North Bridge Core Voltage
CPU Core Voltage Table
P0.9V_AUX 0.9V switched power rail (off in S4-S5) VID(5:0) Voltage VID(5:0) Voltage
P1.2V 1.2V switched power rail (off in S3-S5)
P1.5V 1.5V switched power rail (off in S3-S5) 0 0 0 0 0 0 1.5500 V 1 0 0 0 0 0 0.7625 V
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P1.8V 1.8V switched power rail (off in S3-S5) 0 0 0 0 0 1 1.5250 V 1 0 0 0 0 1 0.7500 V
P1.8V_AUX 1.8V power rail(off in S4-S5) 0 0 0 0 1 0 1.5000 V 1 0 0 0 1 0 0.7375 V
P2.5V 2.5V switched power rail (off in S3-S5) 0 0 0 0 1 1 1.4750 V 1 0 0 0 1 1 0.7250 V
0 0 0 1 0 0 1.4500 V 1 0 0 1 0 0 0.7125 V
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MICOM_P3V 3.3V always on power rail for MICOM 0 0 0 1 0 1 1.4250 V 1 0 0 1 0 1 0.7000 V
P3.3V 3.3V switched power rail (off in S3-S5) 0 0 0 1 1 0 1.4000 V 1 0 0 1 1 0 0.6875 V
0 -
0 0 1 1 1 1.3750 V 1 -
0 0 1 1 1 0.6750 V
0 0 1 0 0 0 1.3500 V 1 0 1 0 0 0 0.6625 V
0 0 1 0 0 1 1.3250 V 1 0 1 0 0 1 0.6500 V
P5V 5.0V switched power rail (off in S3-S5) 0 0 1 0 1 0 1.3000 V 1 0 1 0 1 0 0.6375 V
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0 0 1 0 1 1 1.2750 V 1 0 1 0 1 1 0.6250 V
0 0 1 1 0 0 1.2500 V 1 0 1 1 0 0 0.6125 V
P5V_ALWS 5V power rail (Always On) 0 0 1 1 0 1 1.2250 V 1 0 1 1 0 1 0.6000 V
P3.3V_ALWS 3.3V power rail (Always On) 0 0 1 1 1 0 1.2000 V 1 0 1 1 1 0 0.5875 V
0 0 1 1 1 1 1.1750 V 1 0 1 1 1 1 0.5750 V
P1.5V_ALWS 1.5V power rail (Always On)
0 1 0 0 0 0 1.1500 V 1 1 0 0 0 0 0.5625 V
0 1 0 0 0 1 1.1250 V 1 1 0 0 0 1 0.5500 V
2 0 1 0 0 1 0 1.1000 V 1 1 0 0 1 0 0.5375 V
0 1 0 0 1 1 1.0750 V 1 1 0 0 1 1 0.5250 V
I C / SMB Address
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0 1 0 1 0 0 1.0500 V 1 1 0 1 0 0 0.5125 V
0 1 0 1 0 1 1.0250 V 1 1 0 1 0 1 0.5000 V
Devices Address Hex Bus 0 1 0 1 1 0 1.0000 V 1 1 0 1 1 0 0.4875 V
B 0 1 0 1 1 1 0.9750 V 1 1 0 1 1 1 0.4750 V
B
SB600 Master - SMBUS Master
0 1 1 0 0 0 0.9500 V 1 1 1 0 0 0 0.4625 V
o
W83L786NG(CPU Thermal Sensor) 1001 110X 9Ch Thermal Sensor
0 1 1 0 0 1 0.9250 V 1 1 1 0 0 1 0.4500 V
0 1 1 0 1 0 0.9000 V 1 1 1 0 1 0 0.4375 V
0 1 1 0 1 1 0.8750 V 1 1 1 0 1 1 0.4250 V
0 1 1 1 0 0 0.8500 V 1 1 1 1 0 0 0.4125 V
0 1 1 1 0 1 0.8250 V 1 1 1 1 0 1 0.4000 V
C
0 1 1 1 1 0 0.8000 V 1 1 1 1 1 0 0.3875 V
0 1 1 1 1 1 0.7750 V 1 1 1 1 1 1 0.3750 V
USB PORT Assign
PORT NUMBER ASSIGNED TO
0 SYSTEM PORT A
2, 3 SYSTEM PORT B
4, 5 SYSTEM PORT C
6 DMB
System Power States
A CHP3_SLPS1* S1, Powered-On-Suspend(POS) : In this state, all clocks(except the 32.768KHz clock) are stopped. A
The system context is maintained in system DRAM. Power is maintained to PCI, the CPU, memory controller, memory, and all other criticial subsystems.
Note that this state does not preclude power being removed from non-essential devices, such as disk drives. During this state, CPU can be selected
for either Deep Sleep or Deeper Sleep.
In Deeper Sleep, CPU voltage reduced in this state to reduce the leakage power.
CHP3_SLPS3* S3, Suspend-To-RAM(STR) : The system context is maintained in system DRAM, but power is shut off to non-critical circuits.
SAMSUNG
Memory is retained, and refreshes continue. All clocks stop except RTC clock. ELECTRONICS
CHP3_SLP4S* S4, Suspend-To-Disk(STD) : The Context of the system is maintained on the disk. All power is then shut off to the system except for the logic required to resume.
Externally appears same as S5, but may have different wake events.
CHP3_SLPS5* S5, Soft Off(SOFF) : System context is not maintained. All power is shut off except for the logic required to restart. A full boot is required when waking.
4 3 2 1
4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
P3.3V
D D
10000nF
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