Service Manuals, User Guides, Schematic Diagrams or docs for : Samsung Laptop NP_X60CV01 SAMSUNG NP_X60CV01
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4 3 2 1
T able of C ontents D
S heet 1. C OV E R
SE DONA S heet 2 - 7. DIAG R AM (B lock/P ower) & ANNOT AT IONS
S heet 8. C LOC K G E NE R AT OR
S heet 9 - 11. Y ONAH667 / ME R OM C P U(T B D)
S heet 12. T HE R MAL S E NS OR / F AN C ONT R OL
S heet 13 - 17. C ALIS T OG A-G MC H
S heet18. DDR II S ODIMM
CPU :Intel Y onah667 S heet19. DDR T E R MINAT ION
S heet20 - 23. IC H7-M
Chip Set :Intel Calistoga & ICH7-M S heet24. F WH
S heet25. AT I M56-P G R AP HIC C ONT R OLLE R
Remarks : Mobility Platform S heet29 - 30. V IDE O ME MOR Y C
S heet31. V IDE O S .S / T .S / LD C ONN.
S heet32. DV I C ONT R OLLE R
S heet33 - 34. C R T & S WIT C H
S heet35 - 36. C AR DB US / 1394 / ME DIA C AR D
Model Name : SEDONA S heet37. E XP R E S S C AR D
S heet38. MINE P C I E XP R E S S & DMB
PBA Name : MAIN S heet39. AUDIO C ODE C (AD1986A)
S heet40. AUDIO AG C / AMP
PCB Code : BA41-#####A S heet41. AUDIO WOP E R & AUDIO C ONNE C T OR
S heet42. HDD & ODD C ONNE DT OR & R E MOT E C NT R
Dev. Step : PR S heet43. MIC OM
S heet44 - 45. LAN(Intel 82573E Z)
Revision : 0.81 S heet46. MDC MODE M / US B 0 / LAN C ONN.
S heet47. B 'D T O B 'D C onnector B
T.R. Date : 2005/10/05 S heet48. C HAR G E R
S heet49. P 1.5V _AUX, V C C P
S heet50. MAIN DDR 2 P OWE R
S heet51. C P U V R M(V C C _C OR E )
S heet52. S WIT C HE D P OWE R
DRAW CHECK APPROVAL S heet53. P 3.3V _ALWS & P 5.0V _AUX
S heet54. G R AP HIC C OR E P OWE R / P 1.2V / P 2.5V
S heet55. HDD P AR K , T P M, MOUNT HOLE
S heet56. DOC K ING C ONNE C T OR , S UP E R I/O
S heet57. US B B OAR D
A
Owner : SE C Mobile R & D Signature : X
4
4 3
3 2
2 1
1
TB D
4 3 2 1
D S C HE MA T IC A NNOT A T IONS A ND B OA R D INF OR MA T ION D
P C I Devic es C rys tal / Os c illator
Devices IDS E L# R E Q/G NT # Interrupts TYPE F R E QUE NC Y DE V IC E US AG E
C ardbus AD25 0 A,B ,C C rystal 32.768K Hz IC H7-M R eal T ime C lock
LAN AD21 3 G C rystal 10MHz MIC OM HD64F 2169/2160
MiniP C I S LOT 1 AD23 2 D,E C rystal 14.318MHz C LOC K -G enerator C K -410M
US B AD29(internal) - US B 2.0 #0 : A C rystal 24.576MHz C ardbus C ontroller 1394
US B 2.0 #1 : D C rystal 25MHz LAN Intel LAN
US B 2.0 #2 : C C rystal 27MHz PEG V IDE O (NV 43m)
Hub to P C I AD30(internal) - - 24.576MHz (T B D) HD Audio Audio
LP C bridge/IDE /AC 97/S MB US AD31(internal) B C rystal
-
Internal MAC AD24(internal) - E
AC Link - - B
C P U C ore V oltage T able IMV P -6
V oltage R ails
V DC P rimary DC system power supply (7 to 21V ) Active/Deeper S leep
V C C _C OR E C ore voltage for DOT HAN (1.308~1.068V ) Active Mode Deeper S leep/E xtended Deeper S leep
C Dual Mode R egion C
VTT DOT HAN/ALV IS O P rocessor S ystem B us(P S B ) T ermination (1.05V ) Dual Mode R egion
MC H-M C ore V oltage
V ID(6:0) V oltage V ID(6:0) V oltage V ID(6:0) V oltage
P 0.9V 0.9V switched power rail (off in S 3-S 5)
P 1.2V 1.2V switched power rail (off in S 3-S 5) 0 0 0 0 0 0 0 1.5000 V 0 1 0 1 0 0 0 1.0000 V 1 0 1 0 0 0 1 0.4875 V
P 1.5V 1.5V switched power rail (off in S 3-S 5) 0 0 0 0 0 0 1 1.4875 V 0 1 0 1 0 0 1 0.9875 V 1 0 1 0 0 1 0 0.4750 V
P 1.5V _AUX 1.5V power rail (off in S 4-S 5) 0 0 0 0 0 1 0 1.4750 V 0 1 0 1 0 1 0 0.9750 V 1 0 1 0 0 1 1 0.4625 V
P 1.8V 1.8V switched power rail (off in S 3-S 5) 0 0 0 0 0 1 1 1.4625 V 0 1 0 1 0 1 1 0.9625 V 1 0 1 0 1 0 0 0.4500 V
P 1.8V _AUX 1.8V power rail(off in S 4-S 5) 0 0 0 0 1 0 0 1.4500 V 0 1 0 1 1 0 0 0.9500 V 1 0 1 0 1 0 1 0.4375 V
P 2.5V 2.5V switched power rail (off in S 3-S 5) 0 0 0 0 1 0 1 1.4375 V 0 1 0 1 1 0 1 0.9375 V 1 0 1 0 1 1 0 0.4250 V
0 0 0 0 1 1 0 1.4250 V 0 1 0 1 1 1 0 0.9250 V 1 0 1 0 1 1 1 0.4125 V
MIC OM_P 3V 3.3V always on power rail for MIC OM 0 0 0 0 1 1 1 1.4125 V 0 1 0 1 1 1 1 0.9125 V 1 0 1 1 0 0 0 0.4000 V
P 3.3V 3.3V switched power rail (off in S 3-S 5) 0 0 0 1 0 0 0 1.4000 V 0 1 1 0 0 0 0 0.9000 V 1 0 1 1 0 0 1 0.3875 V
P 3.3V _AUX 3.3V power rail (off in S 4-S 5) 0 0 0 1 0 0 1 1.3875 V 0 1 1 0 0 0 1 0.8875 V 1 0 1 1 0 1 0 0.3750 V
P 3.3V _DT V 3.3V power rail (off in S 4-S 5) 0 0 0 1 0 1 0 1.3750 V 0 1 1 0 0 1 0 0.8750 V 1 0 1 1 0 1 1 0.3625 V
0 0 0 1 0 1 1 1.3625 V 0 1 1 0 0 1 1 0.8625 V 1 0 1 1 1 0 0 0.3500 V
P 5V 5.0V switched power rail (off in S 3-S 5) 0 0 0 1 1 0 0 1.3500 V 0 1 1 0 1 0 0 0.8500 V 1 0 1 1 1 0 1 0.3375 V
P 5V _AUX 5.0V power rail (off in S 4-S 5) 0 0 0 1 1 0 1 1.3375 V 0 1 1 0 1 0 1 0.8375 V 1 0 1 1 1 1 0 0.3250 V
0 0 0 1 1 1 0 1.3250 V 0 1 1 0 1 1 0 0.8250 V 1 0 1 1 1 1 1 0.3125 V
0 0 0 1 1 1 1 1.3125 V 0 1 1 0 1 1 1 0.8125 V 1 1 0 0 0 0 0 0.3000 V
P 3.3V _ALWS 3.3V power rail (Always On)
0 0 1 0 0 0 0 1.3000 V 0 1 1 1 0 0 0 0.8000 V 1 1 0 0 0 0 1 0.2875 V
P 2.5V _ALWS 2.5V power rail (Always On)
0 0 1 0 0 0 1 1.2875 V 0 1 1 1 0 0 1 0.7875 V 1 1 0 0 0 1 0 0.2750 V
P 1.2V _ALWS 1.2V power rail (Always On) 0 0 1 0 0 1 0 1.2750 V 0 1 1 1 0 1 0 0.7750 V 1 1 0 0 0 1 1 0.2625 V
0 0 1 0 0 1 1 1.2625 V 0 1 1 1 0 1 1 0.7625 V 1 1 0 0 1 0 0 0.2500 V
2 0 0 1 0 1 0 0 1.2500 V 0 1 1 1 1 0 0 0.7500 V 1 1 0 0 1 0 1 0.2375 V
0 1 0 1 1 0
I C / S MB A ddres s 0
0
0
0 1
1
0
0
1
1
0
1
1
0
1.2375 V
1.2250 V 0
0
1
1 1
1
1
1
1
1
0
1
1
0
0.7375
0.7250
V
V 1
1
1
1 0
0
0
0
1
1
1
1
0
1
0.2250
0.2125
V
V
0 0 1 1 1 1.2125 V 1 1 1 1 1 0.7125 V 1 1 0 0 0
1 0.2000 V
Devices Address Hex B us
B
B 0 0 1 1 0 0 0 1.2000 V 1 0 0 0 0 0 0 0.7000 V 1 1 0 1 0 0 1 0.1875 V B
B
0 0 1 1 0 0 1 1.1875 V 1 0 0 0 0 0 1 0.6875 V 1 1 0 1 0 1 0 0.1750 V
IC H7 Master - S MB US Master 0 0 1 1 0 1 0 1.1750 V 1 0 0 0 0 1 0 0.6750 V 1 1 0 1 0 1 1 0.1625 V
E MC 6N300(C P U T hermal S ensor) 1001 110X 9C h T hermal S ensor 0 0 1 1 0 1 1 1.1625 V 1 0 0 0 0 1 1 0.6625 V 1 1 0 1 1 0 0 0.1500 V
S ODIMM0 1010 0000 A0h - 0 0 1 1 1 0 0 1.1500 V 1 0 0 0 1 0 0 0.6500 V 1 1 0 1 1 0 1 0.1375 V
S ODIMM1 1010 001X A2h - 0 0 1 1 1 0 1 1.1375 V 1 0 0 0 1 0 1 0.6375 V 1 1 0 1 1 1 0 0.1250 V
C K -408 (C lock G enerator) 1101 001x D2h C lock, Unused C lock Output Disable 0 0 1 1 1 1 0 1.1250 V 1 0 0 0 1 1 0 0.6250 V 1 1 0 1 1 1 1 0.1125 V
0 0 1 1 1 1 1 1.1125 V 1 0 0 0 1 1 1 0.6125 V 1 1 1 0 0 0 0 0.1000 V
0 1 0 0 0 0 0 1.1000 V 1 0 0 1 0 0 0 0.6000 V 1 1 1 0 0 0 1 0.0875 V
0 1 0 0 0 0 1 1.0875 V 1 0 0 1 0 0 1 0.5875 V 1 1 1 0 0 1 0 0.0750 V
0 1 0 0 0 1 0 1.0750 V 1 0 0 1 0 1 0 0.5750 V 1 1 1 0 0 1 1 0.0625 V
0 1 0 0 0 1 1 1.0625 V 1 0 0 1 0 1 1 0.5625 V 1 1 1 0 1 0 0 0.0500 V
US B P OR T A s s ign 0
0
1
1
0
0
0
0
1
1
0
0
0
1
1.0500 V
1.0375 V
1
1
0
0
0
0
1
1
1
1
0
0
0
1
0.5500
0.5375
V
V
1
1
1
1
1
1
0
0
1
1
0
1
1
0
0.0375
0.0250
V
V
0 1 0 0 1 1 0 1.0250 V 1 0 0 1 1 1 0 0.5250 V 1 1 1 0 1 1 1 0.0125 V
P OR T NUMB E R AS S IG NE D T O 0 1 0 0 1 1 1 1.0125 V 1 0 0 1 1 1 1 0.5125 V 1 1 1 1 0 1
0 0 0.0000 V
1 1
0 1 0 0 0 0 0.5000 V 1 1 1 1 0 0 1 0.0000 V
0 S Y S T E M P OR T A 1 1 1 1 0 1 0 0.0000 V
1,2 S Y S T E M P OR T B 1 1 1 1 0 1 1 0.0000 V
Active Deeper S lp
3 S Y S T E M P OR T C 1 1 1 1 1 0 0 0.0000 V
4 B LUE T OOT H DP R S LP V R 0 DP R S LP V R 1 1 1 1 1 1 0 1 0.0000 V
5 P OR T R E P LIC AT OR DP R S T P * 0 1 1 1 1 1 1 0 0.0000 V
6 MINI P C IE XP R E S S F ING E R P R INT DP R S T P * 1 1 1 1 1 1 1 1 0.0000 V
7 E XP R E S S C AR D P S I2* 0 or 1 P S I2* 0 or 1
*"1111111" : 0V power good asserted.
S ystem P ower S tates
A C HP 3_S LP S 1* S 1, P owered-On-S uspend(P OS ) : In this state, all clocks(except the 32.768K Hz clock) are stopped. *Y onah P rocessor (2.33 G Hz / 800 MHz : T B D)
A
T he system context is maintained in system DR AM. P ower is maintained to P C I, the C P U, memory controller, memory, and all other criticial subsystems.
Note that this state does not preclude power being removed from non-essential devices, such as disk drives. During this state, C P U can be selected
for either Deep S leep or Deeper S leep.
In Deeper S leep, C P U voltage reduced in this state to reduce the leakage power.
C HP 3_S LP S 3* S 3, S uspend-T o-R AM(S T R ) : T he system context is maintained in system DR AM, but power is shut off to non-critical circuits.
Memory is retained, and refreshes continue. All clocks stop except R T C clock.
C HP 3_S LP 4S * S 4, S uspend-T o-Disk(S T D) : T he C ontext of the system is maintained on the disk. All power is then shut off to the system except for the logic required to resume.
E xternally appears same as S 5, but may have different wake events.
C HP 3_S LP S 5* S 5, S oft Off(S OF F ) : S ystem context is not maintained. All power is shut off except for the logic required to restart. A full boot is required when waking.
4
4 3
3 2
2
4 3 2 1
P C I4_F C T S E L1(P IN34) P IN 43, 44 P IN 47, 48
0 DOT 96 LC D96/100
P 3.3V
VC C P 1 27MHZ SRC0
B 38
MMZ1608S 121AT
FS A FS B FS C
C 276 10000nF
6.3V
C 277 1000nF
HOS T C LK
C 201 100nF
C 251 100nF
C 278 100nF
10nF
D D
C 279 10nF
CPU B S E L0 B S E L1 B S E L2 R 256 1
10K 1%
10K 1%
C 194 10000nF
0 0 0 266 MHz
10nF
100nF
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