Service Manuals, User Guides, Schematic Diagrams or docs for : Samsung Laptop Samsung_R40HAINAN3_SRE
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4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
D SCHEMATIC ANNOTATIONS AND BOARD INFORMATION D
PCI Devices Voltage Rails
Devices IDSEL# REQ/GNT# Interrupts
Cardbus AD19 0 A,B,C VDC Primary DC system power supply (7 to 21V)
LAN AD21 3 D VCC_CORE Core voltage for BANIAS CPU (1.356 - 0.844V)
MiniPCI SLOT1 AD23 2 E,F VCCP BANIAS/ODEM Processor System Bus(PSB) Termination (1.05V)
USB AD29(internal) - USB2.0 #0 : A VCC_MCH MCH-M Core Voltage (1.2V)
USB2.0 #1 : D
USB2.0 #2 : C P1.5V 1.5V switched power rail (off in S3-S5)
Hub to PCI AD30(internal) - - P1.5V_AUX 1.5V power rail (off in S4-S5)
LPC bridge/IDE/AC97/SMBUS AD31(internal) - B P1.8V 1.8V switched power rail (off in S3-S5)
AGP AD17(internal) - A,B P1.8V_AUX 1.8V power rail(off in S4-S5)
Internal MAC AD24(internal) - E P2.5V 2.5V switched power rail (off in S3-S5)
AC Link - - B P2.5V_AUX 2.5V power rail (off in S4-S5)
P1.25V_AUX 1.25V power rail (off in S4-S5)
MICOM_P3V 3.3V always on power rail for MICOM
P3.3V 3.3V switched power rail (off in S3-S5)
- - P3.3V_AUX 3.3V power rail (off in S4-S5)
PCI SLOT AD20 A,B,C,D
P3.3V_ALWAYS 3.3V always on Power Rail
P5V 5.0V switched power rail (off in S3-S5)
C P5V_ALWAYS 5.0V always on power C
P12V 12.0V switched power rail (off in S3-S5)
CPU Core Voltage Table 2
VID5 VID4 VID3 VID2 VID1 VID0 Voltage VID5 VID4 VID3 VID2 VID1 VID0 Voltage
0 0 0 0 0 0 1.708 V 1 0 0 0 0 0 1.196 V
I C / SMB Address
0 0 0 0 0 1 1.692 V 1 0 0 0 0 1 1.180 V Devices Address Hex Bus
0 0 0 0 1 0 1.676 V 1 0 0 0 1 0 1.164 V
0 0 0 0 1 1 1.660 V 1 0 0 0 1 1 1.148 V ICH4 Master - SMBUS Master
0 0 0 1 0 0 1.644 V 1 0 0 1 0 0 1.132 V ADM1032(CPU Thermal Sensor) 1001 110X 9Ch Thermal Sensor
0 0 0 1 0 1 1.628 V 1 0 0 1 0 1 1.116 V SODIMM0 1010 0000 A0h -
0 0 0 1 1 0 1.612 V 1 0 0 1 1 0 1.100 V SODIMM1 1010 001X A2h -
-
0 0
- 0 1 1 1 1.596 V 1 0
- 0 1 1 1 1.084 V CK-408 (Clock Generator) 1101 001x D2h Clock, Unused Clock Output Disable
0 0 1 0 0 0 1.580 V 1 0 1 0 0 0 1.068 V
0 0 1 0 0 1 1.564 V 1 0 1 0 0 1 1.052 V
0 0 1 0 1 0 1.548 V 1 0 1 0 1 0 1.036 V
0 0 1 0 1 1 1.532 V 1 0 1 0 1 1 1.020 V
0 0 1 1 0 0 1.516 V 1 0 1 1 0 0 1.004 V
0
0
0
0
1
1
1
1
0
1
1
0
1.500 V
1.484 V
1
1
0
0
1
1
1
1
0
1
1
0
0.988 V
0.972 V USB PORT Assign
0 0 1 1 1 1 1.468 V 1 0 1 1 1 1 0.956 V
0 1 0 0 0 0 1.452 V 1 1 0 0 0 0 0.940 V PORT NUMBER ASSIGNED TO
0 1 0 0 0 1 1.436 V 1 1 0 0 0 1 0.924 V
0 1 0 0 1 0 1.420 V 1 1 0 0 1 0 0.908 V 0 SYSTEM PORT A
0 1 0 0 1 1 1.404 V 1 1 0 0 1 1 0.892 V 1 SYSTEM PORT B
B 0 1 0 1 0 0 1.388 V 1 1 0 1 0 0 0.876 V 2 SYSTEM PORT C B
0 1 0 1 0 1 1.372 V 1 1 0 1 0 1 0.860 V 3 FINGER PRINT
0 1 0 1 1 0 1.356 V 1 1 0 1 1 0 0.844 V Lowest Freq. 4 BLUETOOTH
0
- 1 0 1 1 1 1.340 V 1 1 0 1 1 1 0.828 V
0 1 1 0 0 0 1.324 V 1 1 1 0 0 0 0.812 V
Highest Freq. 0 1 1 0 0 1 1.308 V 1 1 1 0 0 1 0.796 V
0 1 1 0 1 0 1.292 V 1 1 1 0 1 0 0.780 V
0
0
1
1
1
1
0
1
1
0
1
0
1.276 V
1.260 V
1
1
1
1
1
1
0
1
1
0
1
0
0.764 V
0.748 V Deeper Sleep System Power States
0 1 1 1 0 1 1.244 V 1 1 1 1 0 1 0.732 V CHP3_SLPS1* S1, Powered-On-Suspend(POS) : In this state, all clocks(except the 32.768KHz clock) are stopped.
0 1 1 1 1 0 1.228 V 1 1 1 1 1 0 0.716 V The system context is maintained in system DRAM. Power is maintained to PCI, the CPU, memory controller, memory, and all other criticial subsystems.
0 1 1 1 1 1 1.212 V 1 1 1 1 1 1 0.700 V Note that this state does not preclude power being removed from non-essential devices, such as disk drives. During this state, CPU can be selected
for either Deep Sleep or Deeper Sleep.
In Deeper Sleep, CPU voltage reduced in this state to reduce the leakage power.
CHP3_SLPS3* S3, Suspend-To-RAM(STR) : The system context is maintained in system DRAM, but power is shut off to non-critical circuits.
Memory is retained, and refreshes continue. All clocks stop except RTC clock.
CHP3_SLP4S* S4, Suspend-To-Disk(STD) : The Context of the system is maintained on the disk. All power is then shut off to the system except for the logic required to resume.
Externally appears same as S5, but may have different wake events.
CHP3_SLPS5* S5, Soft Off(SOFF) : System context is not maintained. All power is shut off except for the logic required to restart. A full boot is required when waking.
REVISION HISTORY
A A
See rev notes in the changes file for more information.
SAMSUNG
ELECTRONICS
4 3 2 1
4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
D D
P3.3V
TP57
1%1% 1%
U513 CY28346 P3.3V
option W320 ICS950810
53 CPU_STOP* VDD_REF 1
P3.3V_AUX 34 PCI_STOP* 8 TP58
VDD_PCI_1 14
TP45 54 S0 VDD_PCI_2 19
TP1585 55 S1 VDD_3V66_1 32
U514 TP44 40 S2 VDD_3V66_2 26
5 7SZ08 VDD_CORE
1 + TP71 VDD_48MHZ 37
4 25 PWR_DWN* VDD_CPU_1 46
2 30 SCLK VDD_CPU_2 50
- 29 SDATA
3
3V66_0 33
51 CPU*0 3V66_1_VCH 35
52 CPU0 21 TP59
66BUFF0_3V66_2 22 TP60
48 CPU*1 66BUFF1_3V66_3 23 TP61
P3.3V 49 CPU1 66BUFF2_3V66_4 24
C No Stuff 66IN_3V66_5 C
P3.3V R171 0 TP53 44 CPU*2 TP62
CLK0_HCLK2* PCI_F0 5
R718 CLK0_HCLK2 R170 0 45 CPU2 PCI_F1 6
10K CLK0_ITP* R172 0 TP52
PCI_F2 7
R719 1% CLK0_ITP R168 0
TP54 No Stuff
28 PWR_GD*
TP63
1.8K
1% PCI0 10 TP64
TP22 2 XTAL_IN PCI1 11 TP65
3 TP55 PCI2 12 TP2311
3 XTAL_OUT PCI3 13 R840 33 1%
CLK3_PCITPM
10K TP56 1%
1 Q23
PCI4 16
TP67 29-A2
1%
1%
1%
MMBT3904 TP21
PCI5 17
OPTION
2 4 GND_REF PCI6 18
9 NO STUFF
682088 15 GND_PCI_1
20 GND_PCI_2 IREF 42
31 GND_3V66_1
GND_3V66_2 DOT 38 TP68
C621 C622 27 GND_CORE USB 39
0.022nF 0.022nF 36 GND_48MHZ
41 GND_IREF 43
MULT0 56 TP1586
NO STUFF 47 GND_CPU REF0
TP69
P/N : 1209-001370 TP70
0.01nF
NO STUFF
B B
C745
SEL1 SEL0 HOST CLK
0 0 66MHz
0 1 100MHz
1 0 200MHz
1 1 133MHz
A A
SAMSUNG
ELECTRONICS
4 3 2 1
4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
D D
VCCP
J508-2
J508-1 2/4
1/4
C25 D15* D47* Y25
AA2 A16* ADS* N2 E23 D14* D46* AA26
Y3 A15* BNR* L1 B23 D13* D45* Y23
AA3 A14* BPRI* J3 C26 D12* D44* V26
U1 N4 E24 U25
DATA GRP 2
Y1 A13* BR0* D24 D11* D43* V24
A12* D10* D42*
DATA GRP 0
Y4 B24 U26
ADDR GROUP 0
W2 A11* A7 C20 D9* D41* AA23
T4 A10* DBR* M2 B20 D8* D40* R23
W1 A9* DBSY* L4 A21 D7* D39* R26
V2 A8* DEFER* H2 B26 D6* D38* R24
R3 A7* DRDY* A24 D5* D37* V23
C V3 A6* B21 D4* D36* U23 C
U4 A5* A22 D3* D35*
P4 A4* HIT* K3 D2* D34* T25
U3 A3* HITM* K4 A25
A19 D1* D33* AA24
Y26
T1 ADSTB0* D25 D0* D32* T24
P1 REQ4* A4 TP72 C23 DINV0* DINV2* W25
T2 REQ3* IERR* B5 C22 DSTBN0* DSTBN2* W24
P3 REQ2* INIT* J2 DSTBP0* DSTBP2*
R2 REQ1* LOCK* M3
REQ0* TRDY* K25 AF26
AF1 N25 D31* D63* AF22
AE1 A31* B11 H26 D30* D62* AF25
AF3 A30* RESET* L2 M25 D29* D61* AD21
A29* RS2* D28* D60*
DATA GRP 3
AD6 A28* RS1* K1 N24 D27* D59* AE21
DATA GRP 1
AE2 A27* RS0* H1 L26 D26* D58* AF20
AD5 J25 AD24
ADDR GROUP 1
AC6 A26* M23 D25* D57* AF23
AB4 A25* D24* D56*
A24* A20M* C2 J23 D23* D55* AE22
LEGENC Y CPU
AD2 A23* FERR* D3 G24 D22* D54* AD23
AE4 A22* IGNNE* A3 F25 D21* D53* AC25
AD3 A21* H24 D20* D52* AC22
AC3 A20* M26 D19* D51* AC20
AC7 A19* LINT0 D1 L23 D18* D50* AB24
AC4 A18* LINT1 D4 G25 D17* D49* AC23
AF4 A17* SMI* B4 H23 D16* D48* AB25
AE5 ADSTB1* STPCLK* C6 J26 DINV1* DINV3* AD20
K24 DSTBN1* DSTBN3* AE24
L24 DSTBP1* DSTBP3* AE25
B B
MT1 MT2 MT3 MT4
RMNT-2.5-1P RMNT-2.5-1P RMNT-2.5-1P RMNT-2.5-1P
A A
SAMSUNG
ELECTRONICS
4 3 2 1
4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS VCC_CORE
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
C541 C542 C540
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF11
AF13
AF15
AF17
AF19
AF21
AF24
AD1
AD4
AD7
AD9
AE3
AE6
AE8
AF2
AF5
AF9
330uF 330uF 330uF
2.5V 2.5V 2.5V
AL AL AL A2 G23
VSS161
VSS162
VSS163
VSS164
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