Service Manuals, User Guides, Schematic Diagrams or docs for : Sony Notebook SONY MBX-165 MS90 - POWER SEQUENCE
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5 4 3 2 1
D 20 18 CPU_PWRGD D
CPU
CPU_RST#
19 PLT_RST#
PWROK
ICH8 15-1 CLK_PWRGD
Crestline VRMPWRGD
SB CK_PWRGD
NB
SLP_S3#
SLP_S4#
SLP_S5#
PM_RSMRST#
PWROK
PWRBTN#
VRMPWRGD
8 7 6 5 4
C
17 C
IMVP_PWRGD 99ms
PWRSW# 3
16 IMVP_OK EC SW
14 IMVP_VR_ON 99ms
15
EC_CLK_EN#IMVP6 13-2 13-1 13 12 11 10 9 2 1
RUN_PWRGD
SUS_ON
ALW_PWRGD 3/5VALW
ALW_ON
RUN_ON2
RUN_ON1
RUN_ON
SUS_PWRGD_10MS
DDR2_PWRGD
11/17:
Check if it's ok to use IMVP_OK to replace
EC_CLK_EN#, it can save one inverter
1_5VRUN
1_25VRUN
1_05VRUN
2_5VRUN
3/5VRUN
1_8VRUN
NV_VDD
PEX_VDD
0_9VSUS
1_8VSUS
1_25VSUS
1_05VSUS
3/5VSUS
CK505
B B
CK_PWRGD/PD#
TI 8402's GRST#
A A
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PLT_RST# NB to CPU
SLP_S3# SB to EC T01(Min=1RTC Max=2RTC refer 21762 T287 Page 328)
SLP_S4# SB to EC T02(Min=1RTC Max=2RTC refer 21762 T291 Page 328)
D D
SLP_S5# SB to EC T03(Min=1RTC Max=2RTC refer 21762 T295 Page 328)
IMVP_PWRGD EC to SB and NB T04(Min=0ms refer 21762 T288 page 328)
BCLK, SRCCLK, PCICLK Running
IMVP_VR_ON EC to IMVP6 T05(Min=1ms 1ms is EC KB3910 at least response time)
IMVP_OK IMVP6 to EC
VRMPWRGD IMVP6 to SB T06(Min=0ms refer 21762 T288 page 328)
T07(Min=20ns refer 21762 T290 page 328)
VHCORE
T08(Min=5ms )
C RUN_ON2 EC output C
T09(Min=15ms )
+1_8VRUN
RUN_ON1 EC output T10(Min=10ms )
PEX_VDD/NV_VDD
T11(Min=10ms )
RUN_ON EC output
RUN_PWRGD Input EC
+3VRUN/ +5VRUN/ +1_5VRUN/+1_25VRUN/+1_05VRUN
T12(Min=10ms )
SUS_PWRGD_10MS EC output
T13(Min=10ms )
SUS_ON EC output
B B
DDR2_PWRGD Input EC
+3VSUS/ +5VSUS/+1_8VSUS/+0.9VSUS
(S5 to G3)
DC_IN
DCBATOUT
ALW_PWRGD
PM_RSMRST#
+5VALW/ +3VALW
T14: RSMRST# falling edge must transition to 0.8V or less before VccSus3_3 drops to 2.1V (Please refer 21762 T312 page 317)
ALW_ON
+ECVCC
PWRSW#
A A
+ECRST#
T01 T02 T03 T04 T05 T06 T07 T08 T09 T10 T11 T12 T13 T14
1 - 2 1 - 2 1 - 2 Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. *1
RTCCLK RTCCLK RTCCLK 0ms 15ms 0ms 20ns 5ms 15ms 10ms 10ms 10ms 10ms
*1 RSMRST# falling edge must transition to 0.8V or less before VccSus3_3 drops to 2.1V
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DC_IN+
MS90 Power On Sequence Timing
DCBATOUT
Version : 0.5
+ECVCC
ECRST# T00
ALW_Power ON when AC in or Batt in only
NOTE : ( EC KB3910 Min. response time is 1ms)
ALW_ON T01 (EC output)
D D
1. T00 : R=47K , C = 0.1uF is ENE recommand value please refer to KB3910B0-AN4A-200
+5VALW/ +3VALW (V5REV_SUS power up befor VccSus3_3, power down
after VccSus3_3. Otherwise tolerance 0.7mv) 2. T01 : 5ms is for ALW VCC supplies must never be active while the ECVCC supply is
inactive.(Please refer to Intel 19513 Page 286 of t200 timing) --> Check(t200 did not say so)
ALW_PWRGD (From MAX8734 (+3VALW & +5VALW) PGOOD to EC) PS : For KB3910 timing : After ECRST# goes to high ,EC must be check sum and initialized
register.For MS01, we measure the T01 Min. 200ms is needed.In MS10 , we will measure this
(Waiting for Power ON) timing again.
T03 (EC initial PWRBTN# by PWRSW# keep low over 15ms)
3. T02 : ALW_PWRGD:H to PM_RSMRST#:H at least 10ms (Refer t204 of Intel 20271 page 304)
PWRSW#
T02 4. T04 : For MS01 SPEC Min. is 50 ms(Normal SPEC is 20ms)
PM_RSMRST# (5ms) T14 (From EC to ICH8) 5. T05 : RSMRST# active High to SLP_S5# active High Max. is 110ms (Refer to t231 of Intel 20271 page 306)
T12 (150ms)
6. T06 : Please reference t233/t234 of Intel 20271 page 306 => Checking
PWRBTN# (700ms) T13 T04(50ms) (From EC to ICH8)
T05 7. T07 : For MS01 current SPEC Min. is 25 ms.--> Checking
8. T08 : For MS01 current SPEC Min. is 1 ms(1ms is EC KB3910 at least response time)
SLP_S5# (From ICH8 to EC)
9. T09 : EC delay 5ms
10.T10 : Please refer to t214 of Intel 20271 page 304
SLP_S4# T06 (From ICH8 to EC)
11.T11 : Please refer to t215 of Intel 20217 page 304
12.T12 : PM_RSMRST# ACTIVE HIGH TO PM_PWRBTN# ACTIVE LOW is 150ms(Normal SPEC is
SLP_S3# T06 (From ICH8 to EC) 110ms;Please reference Intel 16971 Page 301of t232 timing) -->Checking
13.T13 : For MS01 current SPEC Min. is 700 ms(Normal SPEC is 1ms that EC can response)
C SUS_ON (From EC- SLPS4#) T08 EC : SUS_ON goes to Hi after SLP_4# keep Hi 1ms C
14.T14 : For MS01 current SPEC Min. is 5 ms
+3VSUS/ +5VSUS 15.When Powered on, the DDR2 1.8V rail must ramp up from 0 to 1.8V within 2ms. (Refer to Intel 20517 page 441)
16.IMVP_OK is same with SB_PWRGD(reserved And Gate with SYS_PWRGD)
+1_8VSUS/+0_9VSUS/+1_25VSUS/+1_05VSUS (0V to 1.8V -> Max. 2ms for DDR2)
17.In NV4X power sequence : NV_VDD,VRAMVDD,PEX_VDD and VRAM_TERM can ramping up anytime after +3VRUN
starts ramping up.(Please refer to DG-00969_v05c Page 50 for NV4x GPU power sequencing description)
DDR2_PWRGD (From SC486 PGD to EC, but EC no reference this signal now)
18.T15 : Refer ISL6262A Spec no mention.
SUS_PWRGD_10MS T07 19.T16 : Refer ISL6262A Spec page3 PGOOD DELAY.
20.T17 : Refer to ICS9LPR501YGLFT CK505 Spec.
RUN_ON T08 (EC : 1ms)
21.T18 : The ICH8 drives PLTRST# inactive a mininum of 1ms after both PWROK and VRMPWRGD
+3VRUN/ +5VRUN/+1_5VRUN are driven high. (Refer to Intel 20217)
+2_5VRUN/+1_25VRUN/+1_05VRUN
22.CPUPWRGD is an output signal that represents a logical AND of the ICH8's PWROK and VRMPWRGD signals.
RUN_ON1 T09 (EC : 5ms)
23.T20 : From ECRST# L->H to IMVP_PWRGD L->H. If EC's 32KHz is not stable, LPC I/F will
hang. So the 1sec must be guaranteed.(Requested by Doi's san 05/13)
PEX_VDD/NVVDD (For external VGA chip)
RUN_ON2 (EC : 5ms)
B B
+1_8VRUN
RUN_PWRGD (From MAX8743(1_05V & 1_5V) PGOOD to EC)
IMVP_VR_ON T10 (From EC to IMVP_VR's SHUT#)
Remark: (Item1,2,3 add Diode; Item4,5,6 add dischage circuit; Item7 for implement TV)
VHCORE SPEC please refer to Intel 20517 16.7 GMCH/ICH8M Platform Power -up
T15 Requirements)
EC_CLK_EN# (From IMVP6_CLKEN# ) 1. V5REF(+5VRUN) -> +3VRUN, dt:0.7mV
2. V5REF_SUS(+5VALW) -> +3VALW, dt:0.7mV
VRMPWRGD (EC_CLK_EN# inverse to ICH8 VRMPWRGD )
3. +2.5VRUN -> GMCH_VCC(1.05V), dt:0.7mV
High Voltage
4. +1_5VRUN -> +1_05VRUN, dt:0.7mV
CLK_PWRGD (From ICH8M to CK505's CK_PWRGD) dv dv
5. +3.3VRUN -> +2_5VRUN, dt:0.3mV
Low Voltage
IMVP_OK T16 (From IMVP6_PWRGD to EC) 6. +3.3VRUN -> +5VRUN (VccLAN), dt:0.3mV
7. +3_3VRUN -> +1_5VRUN(TV), dt:0.7mV
8. Check +1_05VRUN and VCC1_5_A[25] => Refer Intel 20517 page 438
T20 T00 T01 T02 T03 T04 T05 T06 T07 T08 T09 T10
IMVP_PWRGD (From EC to NB's PWROK & SB's PWROK) R/C delay 1 - 2
A T19 (47K/ Min. Min. Min. Min. Max. RTCCLK Min. Min. Min. A
5 ms 10 ms 40ms 50ms 110ms (Checking) 25 ms 1ms 5ms 99ms
0.1uF)
STPCLK# T11 T12 T13 T14 T15 T16 T17 T18 T19 T20
T11
Max. Min. Min Min TBD Min : 5.5ms Max Min Min : 99ms Min :1s
BCLK, SRCCLK, PCICLK T17 50ns 150ms 700ms 5ms Max : 8.1ms 1.8ms 1ms
Running
CPU_PWRGD (From ICH8 to CPU)
Title
PLT_RST#/ (From ICH8 to GMCH) T18
Size Document Number Rev
C <Doc> <RevCode>
H_CPURST# (From GMCH to CPU)
Date: Tuesday, February 27, 2007 Sheet 1 of 1
5 4 3 2 1
5 4 3 2 1
D Change List D
[V0.2]
1. STPCLK#, CPUSLP#, STP_CPU#/PCI# --> STPCLK#
2. Correct T11 from "IMVP_OK to STPCLK#" --> "IMVP_PWRGD to STPCLK#" (Refer ICH8M EDS T215)
3. Correct down side table T09 from 10ms to 5ms.
4. Correct T18 from "IMVP_OK to PLT_RST#" --> "IMVP_PWRGD to PLT_RST#" (Refer ICH8M ESD)
5. Correct H_CPURST to H_CPURST#
6. Add ICH8M's CK_PWRGD to enable CK505's PWRGD
7. Update CLK_EN# to EC_CLK_EN#
[V0.3]
C C
1. Correct: PWRSW# is driven by EC, not ICH8M
2. Add note: Check if it's ok to use IMVP_OK to replace EC_CLK_EN#, it can save one inverter
[V0.4]
1. Add power off sequence
[V0.5]
1. Correct T12 from min:400ms to 150ms
This modify already phase in MS90-DVT stage.
B B
A A
Title
<Title>
Size Document Number Rev
A <Doc> <RevCode>
Date: Tuesday, February 27, 2007 Sheet 1 of 1
5 4 3 2 1
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