Service Manuals, User Guides, Schematic Diagrams or docs for : TOSHIBA LCD 42LX196 42lx196-02 html x_ref_wire_c

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!M_BL1PWM	c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html	U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_BL0PWM	c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html	U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_SSCLKI	c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html	U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_SDCD	c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html	U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_SDDAT0	c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html	U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_SDDAT1	c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html	U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_SDCMD	c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html	U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_SDCLK	c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html	U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_SDDAT2	c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html	U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_SDWP	c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html	U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_SDDAT3	c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html	U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_UART_KEYREQ	c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html	U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_PIO18	c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html	U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_STC0PWM	c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html	U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_COLDRST	c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html	U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_STC0CLKI	c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html	U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_CLKX	c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html	U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_PIO21	c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html	U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_PIO20	c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html	U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_VBIINT	c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html	U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!V_ACHIPINT1	c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html	U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!S_EUARTINT	c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html	U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!P_LANINT	c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html	U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!D_PODINT	c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html	U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_PIO04	c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html	U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_PIO02	c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html	U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_PIO00	c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html	U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_PIO59	c_u01_seine2[102]sylph_iic_uart_scif(pe0140).html	U01 SEINE2 [102] SYLPH IIC/UART/SCIF (PE0140)
!S_USBCLKXO	c_u01_seine2[102]sylph_iic_uart_scif(pe0140).html	U01 SEINE2 [102] SYLPH IIC/UART/SCIF (PE0140)
!M_UARTCK2	c_u01_seine2[102]sylph_iic_uart_scif(pe0140).html	U01 SEINE2 [102] SYLPH IIC/UART/SCIF (PE0140)
!M_DCHIPIR	c_u01_seine2[102]sylph_iic_uart_scif(pe0140).html	U01 SEINE2 [102] SYLPH IIC/UART/SCIF (PE0140)
!M_UARTCK1	c_u01_seine2[102]sylph_iic_uart_scif(pe0140).html	U01 SEINE2 [102] SYLPH IIC/UART/SCIF (PE0140)
!M_PIO57	c_u01_seine2[102]sylph_iic_uart_scif(pe0140).html	U01 SEINE2 [102] SYLPH IIC/UART/SCIF (PE0140)
!M_UARXD3	c_u01_seine2[102]sylph_iic_uart_scif(pe0140).html	U01 SEINE2 [102] SYLPH IIC/UART/SCIF (PE0140)
!M_PIO58	c_u01_seine2[102]sylph_iic_uart_scif(pe0140).html	U01 SEINE2 [102] SYLPH IIC/UART/SCIF (PE0140)
!M_UATXD3	c_u01_seine2[102]sylph_iic_uart_scif(pe0140).html	U01 SEINE2 [102] SYLPH IIC/UART/SCIF (PE0140)
!M_UARXD2	c_u01_seine2[102]sylph_iic_uart_scif(pe0140).html	U01 SEINE2 [102] SYLPH IIC/UART/SCIF (PE0140)
!M_UATXD2	c_u01_seine2[102]sylph_iic_uart_scif(pe0140).html	U01 SEINE2 [102] SYLPH IIC/UART/SCIF (PE0140)
!M_UATXD1	c_u01_seine2[102]sylph_iic_uart_scif(pe0140).html	U01 SEINE2 [102] SYLPH IIC/UART/SCIF (PE0140)
!M_UATXD0	c_u01_seine2[102]sylph_iic_uart_scif(pe0140).html	U01 SEINE2 [102] SYLPH IIC/UART/SCIF (PE0140)
!M_ACCLK	c_u01_seine2[102]sylph_iic_uart_scif(pe0140).html	U01 SEINE2 [102] SYLPH IIC/UART/SCIF (PE0140)
!M_ACDATA	c_u01_seine2[102]sylph_iic_uart_scif(pe0140).html	U01 SEINE2 [102] SYLPH IIC/UART/SCIF (PE0140)
!M_I2CCLK2	c_u01_seine2[102]sylph_iic_uart_scif(pe0140).html	U01 SEINE2 [102] SYLPH IIC/UART/SCIF (PE0140)
!M_I2CDATA2	c_u01_seine2[102]sylph_iic_uart_scif(pe0140).html	U01 SEINE2 [102] SYLPH IIC/UART/SCIF (PE0140)
!M_UARXD1	c_u01_seine2[102]sylph_iic_uart_scif(pe0140).html	U01 SEINE2 [102] SYLPH IIC/UART/SCIF (PE0140)
!M_UARXD0	c_u01_seine2[102]sylph_iic_uart_scif(pe0140).html	U01 SEINE2 [102] SYLPH IIC/UART/SCIF (PE0140)
!M_I2CDATA0	c_u01_seine2[102]sylph_iic_uart_scif(pe0140).html	U01 SEINE2 [102] SYLPH IIC/UART/SCIF (PE0140)
!M_I2CCLK1	c_u01_seine2[102]sylph_iic_uart_scif(pe0140).html	U01 SEINE2 [102] SYLPH IIC/UART/SCIF (PE0140)
!M_I2CCLK0	c_u01_seine2[102]sylph_iic_uart_scif(pe0140).html	U01 SEINE2 [102] SYLPH IIC/UART/SCIF (PE0140)
!M_I2CDATA1	c_u01_seine2[102]sylph_iic_uart_scif(pe0140).html	U01 SEINE2 [102] SYLPH IIC/UART/SCIF (PE0140)
!M_SBCE5	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBBE1	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBCLK	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBACK	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_PIO28	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_NACLE	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBCE0	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_NAALE	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_NARE	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_NAWE	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBCE1	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_NACE	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBADD4	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBADD5	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBWE	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBADD2	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBBE0	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBADD7	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBADD6	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBADD1	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBADD3	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBOE	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBADD12	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBADD13	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBADD10	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBADD15	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBADD8	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBADD14	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBADD9	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBADD11	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBADD16	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBADD17	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBADD19	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBADD18	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBADD21	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBADD20	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBADD22	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBADD23	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBDAT7	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBDAT4	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBDAT2	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBDAT1	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBDAT6	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBDAT0	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBDAT5	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBDAT3	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBDAT11	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBDAT8	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBDAT10	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBDAT9	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBDAT13	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBDAT12	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBDAT14	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_SBDAT15	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_NABST	c_u01_seine2[103]sylph_sb(pe0140).html	U01 SEINE2 [103] SYLPH SB (PE0140)
!M_CBE0	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_CBE1	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_TRDY	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_IRDY	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_GNT3	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_CBE2	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_GNT1	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PERR	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_STOP	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_SERR	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PAR	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PME	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_FRAME	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_GNT2	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_CBE3	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_DEVSEL	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_GNT0	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_REQ1	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_REQ2	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_REQ0	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_REQ3	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD5	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD12	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD1	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD9	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD6	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD14	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD4	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD10	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD13	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD15	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD11	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD2	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD0	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD8	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD7	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD3	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD20	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD17	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD22	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD18	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD21	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD23	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD19	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD16	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD24	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD26	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD25	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD27	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD28	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD29	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD30	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PCIAD31	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_CLKX	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_COLDRST	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_LOCK	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_IDSEL	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_USBIDSEL	c_u01_seine2[104]sylph_pci(pe0140).html	U01 SEINE2 [104] SYLPH PCI (PE0140)
!M_PIO31	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!M_PIO43	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!M_PIO44	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!DEMO_D7	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!DEMO_D4	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!DEMO_D6	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!DEMO_SYC	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!DEMO_VAL	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!DEMO_D5	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!DEMO_D3	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!DEMO_CLK	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!DEMO_D0	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!DEMO_D2	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!DEMO_D1	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!M_BOARD_TARGET2	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!M_BOARD_TARGET3	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!M_BOARD_TARGET1	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!M_BOARD_TARGET0	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!M_PIO30	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!M_PIO29	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!D_PODTS0	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!D_PODTS3	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!D_PODTS1	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!D_PODTS4	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!D_PLDVLDO	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!D_PODTS5	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!D_PODTS6	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!D_PODTS2	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!D_PLDSYNCO	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!D_PLDCLKO	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!M_PIO47	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!M_PIO49	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!M_PIO45	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!D_PODTS7	c_u01_seine2[105]sylph_ts(pe0140).html	U01 SEINE2 [105] SYLPH TS (PE0140)
!V_RD1_N	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_RD1	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!M_ATXO	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!M_ASDOD	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!M_ABCKOD	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!M_ALRCKOD	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!M_ASDOC3	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!M_ASDOC2	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!M_ASDOC1	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!M_ASDOC0	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!M_ABCKOC	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!M_ALRCKOC	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_TC2	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_TE2	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_TA2_N	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_TCLK2	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_TA2	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_TC2_N	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_TB2_N	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_TB2	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_TD2	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_TE2_N	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_TCLK2_N	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_TD2_N	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!B_DACYO	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_TCLK1_N	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_TCLK1	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_TE1_N	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_TE1	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_TD1_N	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_TD1	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_TC1_N	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_TC1	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_TB1_N	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_TB1	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_TA1_N	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_TA1	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_RCLK1_N	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_RA1_N	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_RC1_N	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_RC1	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_RB1	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_RCLK1	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_RB1_N	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_RA1	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!A_ASDIB	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!A_ALRCKIB	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!A_ABCKIB	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_HDMIBCK	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_HDMIDATA0	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_HDMIDATA1	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!M_AMCLK1	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!M_AMCLK0	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_HDMILRCK	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_HDMIDATA2	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_DACVB	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_VIDINV	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_VIDINH	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_VIDINCLK1	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_DACVREF	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_VIDIN4	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_VIDIN2	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_VIDIN1	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_VIDIN0	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_VIDIN5	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_VIDIN6	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_VIDIN3	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_VIDIN7	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_VIDIN13	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_VIDIN11	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_VIDIN10	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_VIDIN9	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_VIDIN14	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_VIDIN15	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_VIDIN12	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!V_VIDIN8	c_u01_seine2[106]sylph_av(pe0140).html	U01 SEINE2 [106] SYLPH AV (PE0140)
!M_DDRVREF	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRODT0	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRODT1	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQS0	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQS1	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQS2	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQS3	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQS4	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQS5	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQS6	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQS7	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRBA0	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRBA1	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRBA2	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDM0	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDM1	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDM2	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDM3	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDM4	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDM5	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDM6	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDM7	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRWE	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRCAS	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRRAS	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRCS0	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRCS1	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRCKE	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRCLKB0	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRCLK0	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRAD0	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRAD1	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRAD2	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRAD3	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRAD4	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRAD5	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRAD6	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRAD7	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRAD8	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRAD9	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRAD10	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRAD11	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRAD12	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRRODT	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRRDRV	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ8	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ14	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ20	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ9	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ6	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ23	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ28	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ13	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ27	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ15	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ5	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ18	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ19	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ4	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ25	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ24	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ1	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ22	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ30	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ26	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ0	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ12	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ7	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ3	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ29	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ17	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ16	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ21	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ2	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ10	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ11	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ31	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ35	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ32	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ43	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ41	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ37	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ33	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ40	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ44	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ38	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ42	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ47	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ45	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ36	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ39	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ34	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ46	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ53	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ52	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ49	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ48	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ50	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ54	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ55	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ51	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ60	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ61	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ58	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ59	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ57	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ56	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ62	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!M_DDRDQ63	c_u01_seine2[107]sylph_fb(pe0140).html	U01 SEINE2 [107] SYLPH FB (PE0140)
!S_USBCLKXO	c_u01_seine2[120]rst_clk(pe0140).html	U01 SEINE2 [120] RST/CLK (PE0140)
!M_UARTCK2	c_u01_seine2[120]rst_clk(pe0140).html	U01 SEINE2 [120] RST/CLK (PE0140)
!M_UARTCK1	c_u01_seine2[120]rst_clk(pe0140).html	U01 SEINE2 [120] RST/CLK (PE0140)
!M_PCICLK1	c_u01_seine2[120]rst_clk(pe0140).html	U01 SEINE2 [120] RST/CLK (PE0140)
!M_CLKX	c_u01_seine2[120]rst_clk(pe0140).html	U01 SEINE2 [120] RST/CLK (PE0140)
!M_HOSTRST	c_u01_seine2[120]rst_clk(pe0140).html	U01 SEINE2 [120] RST/CLK (PE0140)
!M_COLDRST	c_u01_seine2[120]rst_clk(pe0140).html	U01 SEINE2 [120] RST/CLK (PE0140)
!M_STC0PWM	c_u01_seine2[121]vcxo(pe0140).html	U01 SEINE2 [121] VCXO (PE0140)
!M_SS_EN	c_u01_seine2[121]vcxo(pe0140).html	U01 SEINE2 [121] VCXO (PE0140)
!M_STC0CLKI	c_u01_seine2[121]vcxo(pe0140).html	U01 SEINE2 [121] VCXO (PE0140)
!M_SSCLKI	c_u01_seine2[121]vcxo(pe0140).html	U01 SEINE2 [121] VCXO (PE0140)
!M_PIO31	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_BL_SW	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_PIO44	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_PIO43	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_BLON_OFF	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_PANEL_PWR	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_PIO59	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_LCS	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_AMCLK1DIR	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_SS_EN	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_VBIINT	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_PIO28	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_DB_TIMER	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_EUARTRST	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!V_ACHIPINT1	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_BOARD_TARGET3	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_BOARD_TARGET2	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_DVDSEL	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_PIO58	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_PODRST	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_PIO57	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_PIO29	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_PIO30	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_IRRST	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_VBIRST	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_BOARD_TARGET1	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!S_EUARTINT	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_AMCLK0DIR	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_AMUTE	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_UPDATE	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_PIO49	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_PIO47	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_PIO45	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_PIO18	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!D_PODINT	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!P_LANINT	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_UART_KEYREQ	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_GRESET3	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_PIO20	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_PIO21	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_PIO04	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_BOARD_TARGET0	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_PIO02	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_PIO00	c_u01_seine2[122]pio_irq(pe0140).html	U01 SEINE2 [122] PIO/IRQ (PE0140)
!M_I2CCLK2	c_u01_seine2[123]iic_uart(pe0140).html	U01 SEINE2 [123] IIC/UART (PE0140)
!M_I2CDATA2	c_u01_seine2[123]iic_uart(pe0140).html	U01 SEINE2 [123] IIC/UART (PE0140)
!M_GLTXD	c_u01_seine2[123]iic_uart(pe0140).html	U01 SEINE2 [123] IIC/UART (PE0140)
!M_GLRXD	c_u01_seine2[123]iic_uart(pe0140).html	U01 SEINE2 [123] IIC/UART (PE0140)
!M_VBITX	c_u01_seine2[123]iic_uart(pe0140).html	U01 SEINE2 [123] IIC/UART (PE0140)
!M_VBIRX	c_u01_seine2[123]iic_uart(pe0140).html	U01 SEINE2 [123] IIC/UART (PE0140)
!M_UATXD1	c_u01_seine2[123]iic_uart(pe0140).html	U01 SEINE2 [123] IIC/UART (PE0140)
!M_UARXD1	c_u01_seine2[123]iic_uart(pe0140).html	U01 SEINE2 [123] IIC/UART (PE0140)
!M_UATXD2	c_u01_seine2[123]iic_uart(pe0140).html	U01 SEINE2 [123] IIC/UART (PE0140)
!M_UARXD2	c_u01_seine2[123]iic_uart(pe0140).html	U01 SEINE2 [123] IIC/UART (PE0140)
!M_I2CDEMOD	c_u01_seine2[123]iic_uart(pe0140).html	U01 SEINE2 [123] IIC/UART (PE0140)
!M_I2CDEMOC	c_u01_seine2[123]iic_uart(pe0140).html	U01 SEINE2 [123] IIC/UART (PE0140)
!M_PIO04	c_u01_seine2[123]iic_uart(pe0140).html	U01 SEINE2 [123] IIC/UART (PE0140)
!M_HEAD	c_u01_seine2[123]iic_uart(pe0140).html	U01 SEINE2 [123] IIC/UART (PE0140)
!M_ACCLK	c_u01_seine2[123]iic_uart(pe0140).html	U01 SEINE2 [123] IIC/UART (PE0140)
!M_ACDATA	c_u01_seine2[123]iic_uart(pe0140).html	U01 SEINE2 [123] IIC/UART (PE0140)
!M_UA_TVM2SY	c_u01_seine2[123]iic_uart(pe0140).html	U01 SEINE2 [123] IIC/UART (PE0140)
!M_UARXD0	c_u01_seine2[123]iic_uart(pe0140).html	U01 SEINE2 [123] IIC/UART (PE0140)
!M_UA_SY2TVM	c_u01_seine2[123]iic_uart(pe0140).html	U01 SEINE2 [123] IIC/UART (PE0140)
!M_UATXD0	c_u01_seine2[123]iic_uart(pe0140).html	U01 SEINE2 [123] IIC/UART (PE0140)
!M_I2CCLK1	c_u01_seine2[123]iic_uart(pe0140).html	U01 SEINE2 [123] IIC/UART (PE0140)
!M_I2CDATA1	c_u01_seine2[123]iic_uart(pe0140).html	U01 SEINE2 [123] IIC/UART (PE0140)
!M_I2CCLK0	c_u01_seine2[123]iic_uart(pe0140).html	U01 SEINE2 [123] IIC/UART (PE0140)
!M_I2CDATA0	c_u01_seine2[123]iic_uart(pe0140).html	U01 SEINE2 [123] IIC/UART (PE0140)
!M_SDDAT2	c_u01_seine2[124]serial_ejtag(pe0140).html	U01 SEINE2 [124] SERIAL/EJTAG (PE0140)
!M_SDDAT1	c_u01_seine2[124]serial_ejtag(pe0140).html	U01 SEINE2 [124] SERIAL/EJTAG (PE0140)
!M_SDDAT3	c_u01_seine2[124]serial_ejtag(pe0140).html	U01 SEINE2 [124] SERIAL/EJTAG (PE0140)
!M_SDCMD	c_u01_seine2[124]serial_ejtag(pe0140).html	U01 SEINE2 [124] SERIAL/EJTAG (PE0140)
!M_SDWP	c_u01_seine2[124]serial_ejtag(pe0140).html	U01 SEINE2 [124] SERIAL/EJTAG (PE0140)
!M_SDDAT0	c_u01_seine2[124]serial_ejtag(pe0140).html	U01 SEINE2 [124] SERIAL/EJTAG (PE0140)
!M_SDCLK	c_u01_seine2[124]serial_ejtag(pe0140).html	U01 SEINE2 [124] SERIAL/EJTAG (PE0140)
!M_SDCD	c_u01_seine2[124]serial_ejtag(pe0140).html	U01 SEINE2 [124] SERIAL/EJTAG (PE0140)
!D_JTAGTCK	c_u01_seine2[124]serial_ejtag(pe0140).html	U01 SEINE2 [124] SERIAL/EJTAG (PE0140)
!D_JTAGTMS	c_u01_seine2[124]serial_ejtag(pe0140).html	U01 SEINE2 [124] SERIAL/EJTAG (PE0140)
!D_JTAGTDO	c_u01_seine2[124]serial_ejtag(pe0140).html	U01 SEINE2 [124] SERIAL/EJTAG (PE0140)
!D_JTAGTDI	c_u01_seine2[124]serial_ejtag(pe0140).html	U01 SEINE2 [124] SERIAL/EJTAG (PE0140)
!M_UARXD3	c_u01_seine2[124]serial_ejtag(pe0140).html	U01 SEINE2 [124] SERIAL/EJTAG (PE0140)
!M_UATXD3	c_u01_seine2[124]serial_ejtag(pe0140).html	U01 SEINE2 [124] SERIAL/EJTAG (PE0140)
!M_DDRAD12	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRCKE	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ19	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRBA0	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRCLKB0	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRAD0	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ28	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ18	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRAD2	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ17	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRAD10	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDM2	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRAD5	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRAD4	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRWE	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRAD8	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ27	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRVREF	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ16	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ22	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRAD7	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ31	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ20	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ29	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRAD1	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ26	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRAD6	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQS3	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ21	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRAD11	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRAD9	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRAD3	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ23	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ25	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRCS0	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRRAS	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRCAS	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRBA1	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRODT0	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ24	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRCLK0	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDM3	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQS2	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ30	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRVREF	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQS1	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRODT0	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDM0	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDM1	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQS0	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRCAS	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRWE	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRRAS	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRCS0	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ11	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ10	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ9	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ8	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ14	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ12	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ13	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ15	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ7	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ6	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ5	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ4	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ3	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ2	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ1	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRDQ0	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRCKE	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRCLK0	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRCLKB0	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRBA0	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRBA1	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRAD8	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRAD10	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRAD12	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRAD9	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRAD11	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRAD4	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRAD6	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRAD5	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRAD7	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRAD2	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRAD3	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRAD1	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRAD0	c_u01_seine2[125]ddr2_sdram(low)(pe0140).html	U01 SEINE2 [125] DDR2 SDRAM(LOW) (PE0140)
!M_DDRAD12	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRCKE	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ51	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRBA0	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRCLKB0	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRAD0	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ60	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ50	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRAD2	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ49	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRAD10	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDM6	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRAD5	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRAD4	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRWE	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRAD8	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ59	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRVREF	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ48	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ54	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRAD7	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ63	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ52	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ61	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRAD1	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ58	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRAD6	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQS7	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ53	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRAD11	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRAD9	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRAD3	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ55	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ57	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRCS1	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRRAS	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRCAS	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRBA1	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRODT1	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ56	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRCLK0	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDM7	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQS6	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ62	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRVREF	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQS5	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRODT1	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDM4	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDM5	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQS4	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRCAS	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRWE	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRRAS	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRCS1	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ43	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ42	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ41	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ40	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ46	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ44	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ45	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ47	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ39	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ38	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ37	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ36	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ35	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ34	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ33	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRDQ32	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRCKE	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRCLK0	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRCLKB0	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRBA0	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRBA1	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRAD8	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRAD10	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRAD12	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRAD9	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRAD11	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRAD4	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRAD6	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRAD5	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRAD7	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRAD2	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRAD3	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRAD1	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRAD0	c_u01_seine2[126]ddr2_sdram(high)(pe0140).html	U01 SEINE2 [126] DDR2 SDRAM(HIGH) (PE0140)
!M_DDRODT1	c_u01_seine2[127]terminate(pe0140).html	U01 SEINE2 [127] TERMINATE (PE0140)
!M_DDRCS1	c_u01_seine2[127]terminate(pe0140).html	U01 SEINE2 [127] TERMINATE (PE0140)
!M_DDRCLK0	c_u01_seine2[127]terminate(pe0140).html	U01 SEINE2 [127] TERMINATE (PE0140)
!M_DDRCLKB0	c_u01_seine2[127]terminate(pe0140).html	U01 SEINE2 [127] TERMINATE (PE0140)
!M_DDRRDRV	c_u01_seine2[127]terminate(pe0140).html	U01 SEINE2 [127] TERMINATE (PE0140)
!M_DDRRODT	c_u01_seine2[127]terminate(pe0140).html	U01 SEINE2 [127] TERMINATE (PE0140)
!M_DDRODT0	c_u01_seine2[127]terminate(pe0140).html	U01 SEINE2 [127] TERMINATE (PE0140)
!M_DDRCS0	c_u01_seine2[127]terminate(pe0140).html	U01 SEINE2 [127] TERMINATE (PE0140)
!M_DDRRAS	c_u01_seine2[127]terminate(pe0140).html	U01 SEINE2 [127] TERMINATE (PE0140)
!M_DDRBA0	c_u01_seine2[127]terminate(pe0140).html	U01 SEINE2 [127] TERMINATE (PE0140)
!M_DDRWE	c_u01_seine2[127]terminate(pe0140).html	U01 SEINE2 [127] TERMINATE (PE0140)
!M_DDRBA2	c_u01_seine2[127]terminate(pe0140).html	U01 SEINE2 [127] TERMINATE (PE0140)
!M_DDRBA1	c_u01_seine2[127]terminate(pe0140).html	U01 SEINE2 [127] TERMINATE (PE0140)
!M_DDRCAS	c_u01_seine2[127]terminate(pe0140).html	U01 SEINE2 [127] TERMINATE (PE0140)
!M_DDRAD3	c_u01_seine2[127]terminate(pe0140).html	U01 SEINE2 [127] TERMINATE (PE0140)
!M_DDRAD2	c_u01_seine2[127]terminate(pe0140).html	U01 SEINE2 [127] TERMINATE (PE0140)
!M_DDRCKE	c_u01_seine2[127]terminate(pe0140).html	U01 SEINE2 [127] TERMINATE (PE0140)
!M_DDRAD4	c_u01_seine2[127]terminate(pe0140).html	U01 SEINE2 [127] TERMINATE (PE0140)
!M_DDRCLKB0	c_u01_seine2[127]terminate(pe0140).html	U01 SEINE2 [127] TERMINATE (PE0140)
!M_DDRAD0	c_u01_seine2[127]terminate(pe0140).html	U01 SEINE2 [127] TERMINATE (PE0140)
!M_DDRCLK0	c_u01_seine2[127]terminate(pe0140).html	U01 SEINE2 [127] TERMINATE (PE0140)
!M_DDRAD1	c_u01_seine2[127]terminate(pe0140).html	U01 SEINE2 [127] TERMINATE (PE0140)
!M_DDRAD7	c_u01_seine2[127]terminate(pe0140).html	U01 SEINE2 [127] TERMINATE (PE0140)
!M_DDRAD6	c_u01_seine2[127]terminate(pe0140).html	U01 SEINE2 [127] TERMINATE (PE0140)
!M_DDRAD8	c_u01_seine2[127]terminate(pe0140).html	U01 SEINE2 [127] TERMINATE (PE0140)
!M_DDRAD5	c_u01_seine2[127]terminate(pe0140).html	U01 SEINE2 [127] TERMINATE (PE0140)
!M_DDRAD9	c_u01_seine2[127]terminate(pe0140).html	U01 SEINE2 [127] TERMINATE (PE0140)
!M_DDRAD10	c_u01_seine2[127]terminate(pe0140).html	U01 SEINE2 [127] TERMINATE (PE0140)
!M_DDRAD11	c_u01_seine2[127]terminate(pe0140).html	U01 SEINE2 [127] TERMINATE (PE0140)
!M_DDRAD12	c_u01_seine2[127]terminate(pe0140).html	U01 SEINE2 [127] TERMINATE (PE0140)
!M_DDRVREF	c_u01_seine2[127]terminate(pe0140).html	U01 SEINE2 [127] TERMINATE (PE0140)
!M_SBA3	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBADD1	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBA2	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBADD2	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBADD3	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBA1	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBA4	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBADD4	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBA7	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBADD5	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBA6	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBADD6	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBADD7	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBA5	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBA8	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBADD8	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBA11	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBADD9	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBA10	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBADD10	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBADD11	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBA9	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBA12	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBADD12	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBA15	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBADD13	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBA14	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBADD14	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBADD15	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBA13	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBA16	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBADD16	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBA19	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBADD17	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBA18	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBADD18	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBADD19	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBA17	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBADD20	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (PE0140)
!M_SBADD21	c_u01_seine2[130]pin_config(pe0140).html	U01 SEINE2 [130] PIN CONFIG (P



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