Service Manuals, User Guides, Schematic Diagrams or docs for : TOSHIBA Laptop TOSHIBA_Satellite_T210_-_COMPAL_LA-6031P_NDU00_-_REV_1.0
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A B C D E
1 1
NDU00/NDU10
2
Streamline-S 11.6" 2
Streamline-M 13.3"
LA-6031P REV 1.0 Schematic
3
Intel Arrandale SFF/IBEX PEAK 3
2010-04-12 Rev 1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/04/12 Deciphered Date 2010/01/23 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NDU00_LA-6031P M/B
Date: Monday, April 12, 2010 Sheet 1 of 45
A B C D E
A B C D E
Compal Confidential Clock Generator
Model Name :NDU00/NDU10
Mobile SLG8SP587VTR
page 12
File Name : LA-6031P Arrandale CPU
1
BGA 1288pins 1
Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2
Dual Channel BANK 0, 1, 2, 3 page 11,10
page 5,6,7,8,9 1.5V DDRIII 800/1066 MT/s
USB/B BT conn
FDI X8 DMI X4 USB port 0,1 USB port 5
page 30 page 25
2.7GHz 2.5GHz
3G Int. Camera
USB port 12 USB port 11
USB page 26 page 12
LVDS-A 5V 480MHz
LCD Conn.
page 12
2 2
PCIeMini Card
CRT (Sub-board) RGB
page 13
WiMax
USB
USB port 13
5V 480MHz page 26
PCIe 1x PCIeMini Card
HDMI Level Shifter DDP-C 1.5V 2.5GHz(250MB/s)
HDMI Conn. WLAN
page 14 PCIe port 2
page 26
page 14 Intel Ibex Peak
3G PCIe 1x SATA port 1 SATA HDD0
PCIe port 4 1.5V 2.5GHz(250MB/s) 5V 3GHz(300MB/s) page 24
page 26
SATA port 5
RTL8105E 10/100M PCIe 1x 5V 3GHz(300MB/s)
RJ45+Transformer (Sub-board) FCBGA1071 eSATA USB
PCIe port 1 page 27 1.5V 2.5GHz(250MB/s) USB port 3 USB port 3
page 27 page 24 page 24
3
5V 480MHz 3
Cardreader conn. CardReader JMB389 PCIe 1x
page 28 PCIe port 5 page 28 1.5V 2.5GHz(250MB/s)
page 15~23
SPI
3.3V 33 MHz
LPC BUS
HD Audio 3.3V/1.5V 24MHz
Power/B
HDA Codec
page 33
SPI ROM Debug Port ENE KB926 E0 ALC259
page 29
page 15 page 32 page 31
RTC CKT.
page 15
Touch Pad EC ROM Audio sub-board SPK CONN
4
DC/DC Interface CKT. Int.KBD 4
page 33 page 25 page 32 page 30 page 30
page 34
Security Classification Compal Secret Data Compal Electronics, Inc.
Power Circuit DC/DC Issued Date 2010/04/12 Deciphered Date 2010/01/23 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
page 37~43 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NDU00_LA-6031P M/B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 12, 2010 Sheet 2 of 45
A B C D E
5 4 3 2 1
NSWAA Liverpool Intel Arrandale
NTWAA Sunderland Intel Arrandale B+
Ipeak=5A, Imax=3.5A, Iocp min=8.1 DESIGN CURRENT 5A +5VALW
SUSP
D N-CHANNEL DESIGN CURRENT 4A +5VS D
SI4800
TPS51125RGER
Ipeak=5A, Imax=3.5A, Iocp min=7.9 DESIGN CURRENT 5A +3VALW
WOL_EN#
P-CHANNEL DESIGN CURRENT 330mA +3V_LAN
AO-3413
SUSP
N-CHANNEL DESIGN CURRENT 4A +3VS
SI4800 UMA_ENVDD
P-CHANNEL DESIGN CURRENT 1.5A +LCD_VDD
AO-3413
C BT_PWR# C
DESIGN CURRENT 180mA +BT_VCC
P-CHANNEL
AO-3413
+5VL
+3VL
VR_ON
Ipeak=27A, Imax=18.9A, Iocp min=35
DESIGN CURRENT 48A +CPU_CORE
ADP3211AMNR2G
GFXVR_EN
Ipeak=12A, Imax=8.4A, Iocp min=15.6 DESIGN CURRENT 15A +GFX_CORE
ADP3211AMNR2G
VTTP_EN
Ipeak=20A, Imax=14A, Iocp min=28.72 DESIGN CURRENT 18A +VTT/+1.05VS
B B
APW7138NITRL
SYSON
Ipeak=7.5A, Imax=5.25A, Iocp min=9.67 DESIGN CURRENT 7.5A +1.5V
RT8209BGQW
SUSP
DESIGN CURRENT 3A +1.5VS_CPU_VDDQ
SI4856ADY
SUSP
DESIGN CURRENT 1.5A +0.75VS
G2992F1U
SUSP
N-CHANNEL DESIGN CURRENT 1.2A +1.5VS
SI4800BDY
A SUSP# A
Ipeak=1.7A, Imax=1.19A, Iocp min=3 DESIGN CURRENT 1.5A +1.8VS
MP2121DQ-LF-Z
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/04/12 Deciphered Date 2010/01/23 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Tree
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NDU00_LA-6031P M/B
Date: Monday, April 12, 2010 Sheet 3 of 45
5 4 3 2 1
A B C D E
( O MEANS ON X MEANS OFF )
Voltage Rails BTO Option Table
+RTCVCC +B +5VALW +1.5V +5VS Function Bluetooth HDMI 3G Mini Card Mini Card Gensor
+5VL +3VALW +3VS
main 2nd
+3VL +1.5VS
1 power explain Bluetooth HDMI 3G WIRELESS WIMAX 1
plane +GFX_CORE R5F211B4D31SP R5F211B4D34SP
+CPU_CORE
GSENSOR@ GSENSOR@
+VTT
1STGSENSOR@ 2NDGSENSOR@
+0.75VS BTO BT@ IHDMI@ 3G@ WLAN@ WIMAX@
1ST@ 2ND@
+1.8VS
+1.5VS_CPU_VDDQ
State
SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5#
Full ON HIGH HIGH HIGH
S0 S1(Power On Suspend) HIGH HIGH HIGH
O O O O O
S3 (Suspend to RAM) LOW HIGH HIGH
2 S1 2
O O O O O
S4 (Suspend to Disk) LOW LOW HIGH
S3
O O O O X S5 (Soft OFF) LOW LOW LOW
S5 S4/AC G3 LOW LOW LOW
O O O X X
S5 S4/ Battery only
O O X X X
S5 S4/AC & Battery
don't exist
O X X X X
3 3
EC SM Bus1 address EC SM Bus2 address
Power Device Address Power Device Address
+3VL EC KB926 D3 +3VS EC KB926 D3
+3VL Smart Battery 0001 011x b
+3VS Gensor
+3VS PCH 0100 110x b
PCH SM Bus address
Power Device Address
+3VALW PCH
+3VS Clock Generator 1101 001x b
4 +3VS DDR DIMM0 1001 000x b 4
+3VS DDR DIMM1 1001 010x b
+3VS WLAN/Wimax/3G
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/04/12 Deciphered Date 2010/01/23 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NDU00_LA-6031P M/B
Date: Monday, April 12, 2010 Sheet 4 of 45
A B C D E
5 4 3 2 1
U1B
Layout rule 10mil width 1 2 H_COMP3 AD71
For S3 CPU power saving
R1 20_0402_1% COMP3
trace length < 0.5", BCLK AK7 CLK_CPU_BCLK 20 2 1
Misc
Misc
1 2 H_COMP2 AC70 AK8 CLK_CPU_BCLK# 20 R2 @ 0_0402_5%
spacing 20mil R3 20_0402_1% COMP2 BCLK#
1 2 H_COMP1 AD69 K71 CLK_CPU_XDP_R 1 2 CLK_CPU_XDP
COMP1 BCLK_ITP
Clocks
R4 49.9_0402_1% J70 CLK_CPU_XDP#_R 1 R5 @ 2 0_0402_5% CLK_CPU_XDP#
BCLK_ITP#
S
D
1 2 H_COMP0 AE66 R6 @ 0_0402_5% SM_DRAMRST#_CPU 3 1
COMP0 SM_DRAMRST# 10,11
R7 49.9_0402_1% L21 CLK_PEG 16 PS@
PEG_CLK
1
J21 CLK_PEG# 16 Q1
TP_SKTOCC# M71 PEG_CLK# PS@ BSS138_NL_SOT23-3
G
PAD T1
2
+VTT PROC_DETECT R8
DPLL_REF_SSCLK Y2
W4 100K_0402_5% 2 R1484 1 RST_GATE 20
CATERR# DPLL_REF_SSCLK# 0_0402_5%
D 1 2 N61 1 D
2
R9 49.9_0402_1% CATERR# PS@
C878
Thermal
Thermal
SM_DRAMRST# BJ12 SM_DRAMRST#_CPU 0.1U_0402_10V6K
N19 2 PS@ +VTT
20 PECI PECI
SM_RCOMP[0] BV33 SM_RCOMP_0 R10 1 2 100_0402_1%
SM_RCOMP[1] BP39 SM_RCOMP_1 R12 1 2 24.9_0402_1% DDR3 Compensation Signals
Layout Note:Please these
SM_RCOMP[2] BV40 SM_RCOMP_2 R14 1 2 130_0402_1% resistors near Processor
PM_EXTTS#0 R13 2 1 10K_0402_5%
DDR3
Misc
+VTT 1 2 H_PROCHOT#_D N67 PROCHOT#
R11 68_0402_5%
PM_EXT_TS#[0] AV66 PM_EXTTS#0 PM_EXTTS#_R R17 2 1 10K_0402_5%
PM_EXT_TS#[1] AV64 PM_EXTTS#_R 2 1 PM_EXTTS# 10,11
R18 0_0402_5% XDP_TDI_R 1 2 XDP_TDI
+VTT N17 R20 0_0402_5%
20 H_THERMTRIP# THERMTRIP#
XDP_TDO_M 1 @ 2 XDP_TDO
2 @ 1 U71 XDP_PRDY# R22 0_0402_5%
19,26,27,28,31,32 PLT_RST# PRDY#
2
1
0_0402_5% R19 U69 XDP_PREQ#
R15 PREQ# R24
68_0402_5% XDP_RST#_R 1 2 H_CPURST# N70 T67 XDP_TCK 0_0402_5%
R21 1K_0402_5% RESET_OBS# TCK XDP_TMS
@ TMS N65
Power Management
Power Management
1 2 H_PMSYNCH M17 P69 XDP_TRST# Routed as a single daisy chain
17 PMSYNCH
1
2
R23 0_0402_5% PM_SYNC TRST# XDP_TDI_M 1 @ 2
H_CPURST# T69 XDP_TDI_R R27 0_0402_5%
TDI XDP_TDO_R
TDO T71
P71 XDP_TDI_M 2 1 XDP_TDO_R 1 2
TDI_M +3VS
JTAG & MBP
2 1 H_PWRGOOD1_R AM7 VCCPW RGOOD_1 TDO_M T70 XDP_TDO_M R25 1K_0402_5% R29 0_0402_5%
0_0402_5% R26
+1.5VS_CPU_VDDQ W 71 JTAG MAPPING
DBR# XDP_DBRESET# 17
H_PWRGOOD 2 1 H_PWRGOOD0_R Y67
20 H_PWRGOOD VCCPW RGOOD_0
C 0_0402_5% R28 C
J69 XDP_BPM#0 Scan Chain STUFF -> R20, R23, R27
BPM#[0]
2
DRAMPWROK 2 1 DRAMPWROK_R AM5 J67 XDP_BPM#1 (Default) NO STUFF -> R21, R26
17 DRAMPWROK SM_DRAMPW ROK BPM#[1]
R30 0_0402_5% R31 J62 XDP_BPM#2 EMI reverse, close to CPU
1.1K_0402_1% BPM#[2] XDP_BPM#3
BPM#[3] K65
@
39 VTTPWROK_CPU
VTTPWROK_CPU H15 K62 XDP_BPM#4 CPU Only STUFF -> R20, R21
VTTPW RGOOD BPM#[4] XDP_BPM#5 XDP_BPM#0 @ R1431 1 0_0402_5% XDP_BPM#0_R NO STUFF -> R23, R26, R27
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