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A B C D E
1 1
Compal Confidential
2 2
Buffalo KAVAA
LA-5121P Schematics Document
Intel Diamondville Processor/ Calistoga(945GSE)/ ICH7M
3
2009-03-10 3
REV: 1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/11/17 Deciphered Date 2009/11/17 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C ustom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KAVAA LA-5121P M/B
D ate: Tuesday, March 10, 2009 Sheet 1 of 42
A B C D E
A B C D E
Compal Confidential
Model Name : KAVAA Fan Control Intel Diamondville SC Thermal Sensor Clock Generator
page 28
File Name : LA-5121P EMC1402 SLG8SP556VTR
FCBGA8-437 Pins page 4 page 12
1
(22x22mm) page 4,5
1
FSB
H_A#(3..31) 400/533MHz H_D#(0..63)
CRT Conn. Intel Calistoga GSE
page 14
Memory BUS(DDRII) 200pin DDRII-SO-DIMM
FCBGA998 page 11
LED Conn. LVDS
page 13 ONE CHANNEL (27x27mm) 1.8V DDRII 400/533
page 6,7,8,9,10
2
DMI x 2 USB Conn X3 Int. Camera 2
PCIeMini Card PCIeMini Card USB port 0,2,7 USB port 1
WiMax 3G page 20 page 21
USB port 4 USB port 5 USB USB
page 19 page 19
5V 480MHz 5V 480MHz BT conn Touch Screen conn
PCIeMini Card PCIeMini Card USB port 6 BTO USB port 4 ,5
PCIe 1x [2,4]
WLAN GPS 1.5V 2.5GHz(250MB/s)
Intel ICH7M page 21 page 20
PCIe port 2 USB port 5
page 19 page 19
BGA-652
PCIe 1x
(31x31mm)
RJ45 RTL8103EL 10/100M 1.5V 2.5GHz(250MB/s)
page 24
SATA port 0 SATA HDD&SSD
PCIe port 3 page 24 5V 1.5GHz(150MB/s)
page 21
USB page 15,16,17,18
3
Card Reader 3
RTS5159 2IN1 5V 480MHz
RTC CKT.
page 16 USB port 3 page 25 3.3V 24.576MHz/48Mhz
HD Audio
3.3V 33 MHz
LPC BUS
DC/DC Interface CKT. HDA Codec
page 30 ALC272-GR
page 22
Debug Port ENE KB926 D3
Power Circuit DC/DC page 28 page 26
AMP.
page 31~37 Int.
MIC CONN MIC CONN HP CONN TPA6017
page 23 page 23 page 23 page 23
Touch Pad Int.KBD SPI ROM GSENSOR
page 29 page 28 page 28 page 27
4 Power/B SPK CONN 4
page 29 page 23
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/11/17 Deciphered Date 2009/11/17 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KAVAA LA-5121P M/B
D ate: Tuesday, March 10, 2009 Sheet 2 of 42
A B C D E
A B C D E
Voltage Rails
1 SIGNAL 1
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Power Plane Description S1 S3 S5 G3
Full ON HIGH HIGH HIGH ON ON ON ON
VIN Adapter power supply (19V) ON ON ON OFF
B+ AC or battery power rail for power circuit. ON ON ON ON S1(Power On Suspend) HIGH HIGH HIGH ON ON ON LOW
+CPU_CORE Core voltage for CPU ON OFF OFF OFF
S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF OFF
+1.05VS VCCP switched power rail ON OFF OFF OFF S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF OFF
S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
+1.8V 1.8V power rail for DDR ON ON OFF OFF
+2.5VS 2.5V switched power rail ON OFF OFF OFF
+3VALW 3.3V always on power rail ON ON ON OFF
+3V_SB 3.3V power rail for LAN ON ON OFF OFF
+3V_LAN 3.3V power rail for LAN ON ON OFF OFF
BTO Option Table
+3V_WLAN 3.3V power rail for LAN ON ON OFF OFF
2 2
+3VS 3.3V switched power rail ON ON OFF OFF
+5VALW 5V always on power rail ON OFF ON OFF Function Mini PCI-E SLOT CAMERA & MIC BLUE TOOTH STAR G-SENSOR
+5V_SB 5V power rail for SB ON ON OFF OFF
+5VS 5V switched power rail ON OFF OFF ON
description
+VSB VSB always on power rail ON ON ON OFF explain Wi-Fi WiMax 3GGPS 3G CAMERA MIC BLUE TOOTH POWER SAVING HDD PROTECT
+RTCVCC RTC power ON ON ON OFF
BTO WLAN@ WIMAX@ 3GGPS@ 3G@ CAM@ MIC@ BT@ STAR@ GSENSOR@
Function
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
description
explain
BTO
3 3
EC SM Bus1 address EC SM Bus2 address
Device Address Device Address
Smart Battery 0001 011X b EMC1402 1001 010X b
ICH7M SM Bus address
Device Address
Clock Generator 1101 001Xb
(SLG8SP556VTR)
DDR DIMMA 1010 000Xb
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/11/17 Deciphered Date 2009/11/17 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C ustom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KAVAA LA-5121P M/B
D ate: Tuesday, March 10, 2009 Sheet 3 of 42
A B C D E
5 4 3 2 1
<6> H_A#[3..16]
U1A
+1.05VS +1.05VS <6> H_D#[0..15] H_D#[32..47] <6>
H_A#3 P21 V19 H_ADS# H_ADS# <6> U1B
H_A#4 A[3]# ADS# H_ BNR# H _D#0 H_D#32
H20 A[4]# BNR# Y19 H_BNR# <6> Y11 D[0]# D[32]# R3
H_A#5 N20 U21 H_B PRI# H_BPRI# <6> H _D#1 W10 R2 H_D#33
A[5]# BPRI# D[1]# D[33]#
1
1
H_A#6 R20 H _D#2 Y12 P1 H_D#34
A[6]# D[2]# D[34]#
0
GROUP
ADDR
H_A#7 J19 T21 H_D EFER# R1 R2 H _D#3 AA14 N1 H_D#35
A[7]# DEFER# H_DEFER# <6> D[3]# D[35]#
DATA GRP 0
H_A#8 N19 T19 H _ D R DY# H _ D R DY# <6> 56_0402_5% 330_0402_5% H _D#4 AA11 M2 H_D#36
H_A#9 A[8]# DRDY# H_DBSY# H _D#5 D[4]# D[36]# H_D#37
G20 A[9]# DBSY# Y18 H_DBSY# <6> W12 D[5]# D[37]# P2
H_A#10 M19 H _D#6 AA16 J3 H_D#38
2
2
H_A#11 A[10]# H_BR0# H _D#7 D[6]# D[38]# H_D#39
H21 T20 Y10 N3
DATA GRP 2
A[11]# BR0# H_BR0# <6> D[7]# D[39]#
H_A#12 L20 H _D#8 Y9 G3 H_D#40
A[12]# D[8]# D[40]#
CONTROL
D H_A#13 M20 F16 H_IER R# H _D#9 Y13 H2 H_D#41 D
H_A#14 A[13]# IERR# H_IN IT#_R R3 1 D[9]# D[41]#
K19 A[14]# INIT# V16 2 1K_0402_5% H_INIT# <16>
H_D#10 W15 D[10]# D[42]# N2 H_D#42
H_A#15 J20 H_D#11 AA13 L2 H_D#43
A[15]# D[11]# D[43]#
H_A#16 L21 A[16]# LOCK# W20 H_LOCK# H_LOCK# <6> Close to CPU H_D#12 Y16 D[12]# D[44]# M3 H_D#44
H_ADSTB#0 K20 H_D#13 W13 J2 H_D#45
<6> H_ADSTB#0 ADSTB[0]# D[13]# D[45]#
T1 H_AP0 D17 D15 H_RESET# H_RS#[0..2] <6> H_D#14 AA9 H1 H_D#46
<6> H_REQ#[0..4] AP0 RESET# H_RESET# <6> D[14]# D[46]#
PAD H_REQ#0 N21 W18 H_RS#0 H_D#15 W9 J1 H_D#47
H_REQ#1 REQ[0]# RS[0]# H_RS#1 H_DSTBN#0 D[15]# D[47]# H_DSTBN#2
J21 REQ[1]# RS[1]# Y17 <6> H_DSTBN#0 Y14 DSTBN[0]# DSTBN[2]# K2 H_DSTBN#2 <6>
H_REQ#2 G19 U20 H_RS#2 <6> H_DSTBP#0 H_DSTBP#0 Y15 K3 H_DSTBP#2 H_DSTBP#2 <6>
H_REQ#3 REQ[2]# RS[2]# H_TRDY# H_DINV#0 DSTBP[0]# DSTBP[2]# H_DINV#2
P20 REQ[3]# TRDY# W19 H_TRDY# <6> <6> H_DINV#0 W16 DINV[0]# DINV[2]# L1 H_DINV#2 <6>
H_REQ#4 R19 H_DP#0 V9 M4 H_DP#2
REQ[4]# H _HIT# T2 PAD DP#0 DP#2 PAD T3
<6> H_A#[17..31] HIT# AA17 H_HIT# <6> <6> H_D#[16..31] H_D#[48..63] <6>
H_A#17 C19 V20 H_HITM# H_HITM# <6> H_D#16 AA5 C2 H_D#48
H_A#18 A[17]# HITM# H_D#17 D[16]# D[48]# H_D#49
F19 A[18]# Y8 D[17]# D[49]# G2
H_A#19 E21 K17 H_D#18 W3 F1 H_D#50
H_A#20 A[19]# BPM[0]# H_D#19 D[18]# D[50]# H_D#51
A16 A[20]# BPM[1]# J18 U1 D[19]# D[51]# D3
H_A#21 D19 H15 H_D#20 W7 B4 H_D#52
A[21]# BPM[2]# D[20]# D[52]#
DATA GRP 1
H_A#22 C14 J15 H_D#21 W6 E1 H_D#53
A[22]# BPM[3]# D[21]# D[53]#
ADDR GROUP 1
H_A#23 C18 K18 H_D#22 Y7 A5 H_D#54
H_A#24 A[23]# PRDY# PREQ# H_D#23 D[22]# D[54]# H_D#55
C20 A[24]# PREQ# J16 AA6 D[23]# D[55]# C3
XDP/ITP SIGNALS
H_A#25 E20 M17 ITP_TCK H_D#24 Y3 A6 H_D#56
DATA GRP 3
H_A#26 A[25]# TCK ITP_TDI H_D#25 D[24]# D[56]# H_D#57
D20 A[26]# TDI N16 W2 D[25]# D[57]# F2
H_A#27 B18 M16 ITP_TDO H_D#26 V3 C6 H_D#58
H_A#28 A[27]# TDO ITP_TMS H_D#27 D[26]# D[58]# H_D#59
C15 A[28]# TMS L17 U2 D[27]# D[59]# B6
H_A#29 B16 K16 ITP_TRST# H_D#28 T3 B3 H_D#60
H_A#30 A[29]# TRST# H_D#29 D[28]# D[60]# H_D#61
B17 A[30]# BR1# V15 AA8 D[29]# D[61]# C4
H_A#31 C16 H_D#30 V2 C7 H_D#62
H_A#32 A[31]# H_PROCHOT#_R H_D#31 D[30]# D[62]# H_D#63
A17 A[32]# PROCHOT# G17 1 2 H_PROCHOT# <37> W4 D[31]# D[63]# D2
H_A#33 B14 E4 H_THERMDA R4 22_0402_5% H_DSTBN#1 Y4 E2 H_DSTBN#3 H_DSTBN#3 <6>
<6> H_DSTBN#1
THERM
A[33]# THRMDA DSTBN[1]# DSTBN[3]#
C H_A#34 B15 A[34]# THRMDC E5 H _THERMDC Close to CPU <6> H_DSTBP#1
H_DSTBP#1 Y5 DSTBP[1]# DSTBP[3]# F3 H_DSTBP#3 H_DSTBP#3 <6>
C
H_A#35 A14 H_DINV#1 Y6 C5 H_DINV#3
A[35]# <6> H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 <6>
H_ADSTB#1 B19 H17 H_THERMTRIP# H_THERMTRIP# <6,16> H_DP#1 R4 D4 H_DP#3
<6> H_ADSTB#1 ADSTB[1]# THERMTRIP# DP#1 DP#3
H_AP1 M18 T4 PAD PAD T5
T6 PAD AP1 COMP0 R5 27.4_0402_1%
+CPU_GTLREF A7 GTLREF COMP[0] T1 1 2
H_A20M# U18 R6 1 @ 2 1K_0402_5% ACLKPH U5 T2 COMP1 1 R7 2 54.9_0402_1%
<16> H_A20M# A20M# ACLKPH COMP[1]
H_FE RR# T16 V11 CLK_CPU_BCLK CLK_CPU_BCLK <12> R8 1 @ 2 1K_0402_5% DCL KPH V5 F20 COMP2 2 R9 1 27.4_0402_1%
<16> H_FERR# FERR# BCLK[0] DCLKPH COMP[2]
H_IG NNE# J4 V12 CLK_CPU_BCLK# T17 F21 COMP3 2 R10 1 54.9_0402_1%
<16> H_IGNNE# IGNNE# BCLK[1] CLK_CPU_BCLK# <12> BINIT# COMP[3]
H_STPCLK# R16 R6 MISC
<16> H_STPCLK# H_IN TR STPCLK# EDM H_DPRSTP#
<16> H_INTR T15 +CPU_EXTBGREF M6 R18 H_DPRSTP# <16,37>
H CLK
H_N MI LINT0 EXTBGREF DPRSTP# H_DPSLP#
<16> H_NMI R15 LINT1 N15 FORCEPR# DPSLP# R17 H_DPSLP# <16>
H_SMI# U17 N6 U4 H _DPW R# H_DPW R# <6>
<16> H_SMI# SMI# HFPLL DPWR# H_PW RGOOD
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