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A B C D E
1 1
LA-1641 REV0.2 Schematic
2 2
Document P4 uFCBGA/uFCPGA Northwood
Intel Mobile Celeron
with Montara GML / ICH4-M / Integrated VGA
2002-11-20
3 3
4 4
Title
Compal Electronics, Ltd.
Cover P age
Size Document Number Rev
CustomLA-1641 0.3
Date: Monday, November 25, 2002 Sheet 1 of 46
A B C D E
A B C D E
COMPAL CONFIDENTIAL
REV:0.3
1 1
CPU
Thermal CLOCK
Mobile P4 ICS950810
sensor Northwood Celeron PAGE 15
PAGE 4 478 uFCPGA
PAGE 4, 5, 6
PSB
CHRONTEL 7011 DVO#C
TV-OUT Controller
DVO BUS
PAGE 14 Montara GML
LVDS&DAC Interface
VGA Embeded MEMORY BUS DDR DIMM X 2 DC/DC Interface
CRT & LVDS 732 uFCBGA
Connector PAGE 38
PAGE 11
2 2
PAGE 13
PAGE 7,8,9,10
HUB Li nk
INTERNALIDE
OZ-168 PCI BUS
IDSEL: AD18 IDSEL: AD20 IDSEL: AD17 IDSEL: AD16
PAGE 25
MASTER 1 MASTER 2 MASTER 3 MASTER 3
PIRQC#, PIRQD# SIRQ,(PIRQE#, PIRQF#) PIRQB# PIRQA#
(PIRQG#, PIRQH#) PIRQA#, PIRQB# (PIRQD)
INTERNALIDE Secondary IDE
HDD/
CD-ROM Mini PCI
Primary IDE
Connector CARDBUS LAN Controller 1394 Controller
PAGE 26
ICH4-M OZ6933 RTL8100BL VIA 6307S
PAGE 24 PAGE 20 PAGE 22 PAGE 19
421 BGA
AC LINK
USB 2.0 Port X 4/
BlueTooth connector
3 3
PAGE 16,17,18
PAGE 29
MDC PCMCIA RJ45/RJ11
Connector SOCKET Connector
LPC
LPC
LPC PAGE 27 PAGE 21 PAGE 23
POWER INTERFACE
SD Reader B+
AUDIO Audio AMP
Winbond Super I/O EC/KBC AC97 Codec +CPU_CORE
W83L518D LPC-47N227 PC87591 ALC202 HARDWARE TPA0232 +2.5VP
PAGE 33 PAGE 28 PAGE 34 PAGE 30 EQ PAGE 31 PAGE 32 +1.5VALWP
+12VALWP
+5VALWP
+3VALWP
PowerGood Interface/ +1.25VSP
System Connector +1.2VPP
+1.2VSP
4 BIOS/ PAGE 36, 37
PAGE 39, 40, 41, 42, 43, 44 4
Parallel PORT Ext. I/O
PAGE 27 PAGE 35
Title
Compal Electronics, Ltd.
Cover P age
Size Document Number Rev
CustomLA-1641 0.3
Date: Monday, November 25, 2002 Sheet 2 of 46
A B C D E
A B C D E
Voltage Rails SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
Power Plane Description S1 S3 S5
S 1 ( P o wer On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
1
V IN Adapter power supply (19V) N/A N/A N/A 1
S 3 ( S uspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
+CPU_VCC Core voltage for CPU ON OFF OFF S 4 ( S uspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+1.2VP 1.2V switched power rail for CPU AGTL Bus ON OFF OFF
S 5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.2VS 1.2V switched power rail for Montara core ON OFF OFF
+1.25VS 1.25V switched power rail ON OFF OFF
+1.5VS AGP 4X ON OFF OFF
+2.5V 2.5V power rail ON ON OFF
+2.5VS 2.5V switched power rail ON OFF OFF Board ID Table for AD channel
+3VALW 3.3V always on power rail ON ON ON*
+3V 3.3V power rail ON ON OFF Vcc 3.3V +/- 5%
+3VS 3.3V switched power rail ON OFF OFF Ra 100K +/- 5%
+5VALW 5V always on power rail ON ON ON* Board ID
Rb VAD_BID min VAD_BID typ VAD_BID max
+5V 5V power rail ON ON OFF 0 0 0 V 0 V 0 V
+5VS 5V switched power rail ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+12VALW 12V always on power rail ON ON ON* 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
2
RTCVCC RTC power ON ON ON 3 33K +/- 5% 0.712 V 0.819 V 0.875 V 2
4 56K +/- 5% 1.036 V 1.185 V 1.264 V
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
Note : ON* means that this power plane is ON only with AC power available, other wise it is OFF. 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
External PCI Devices 7 NC 2.500 V 3.300 V 3.300 V
D e v ice IDSEL# REQ#/GNT# Interrupts
Board ID PCB Revision
CardBus AD20 2 PIRQA/PIRQB(PIRQE/PIRQF) 0 0.1
LAN AD17 3 PIRQB(PIRQD) 1 0.2
Mini-PCI AD18 1/1 PIRQC/PIRQD(PIRQG/PIRQH) 2 0.3
1394 AD16 0 PIRQA 3 0.4
4 0.5
5 0.6
6 0.7
7 0.8
EC SM Bus1 address EC SM Bus2 address
3 3
D e v ice Address Device Address Sapporo Z to ZJ BOM modify list :
Smart Battery 0001 011X b ADM1032 1001 110X b 1 . Remove R594
EEPROM(24C16/02) 1010 000X b OZ168 0011 0100 b 2 .Add R112
(24C04) 1011 000Xb Smart Battery 0001 011X b
Docking 0011 011X b
DOT Board XXXX XXXXb
ICH4 SM Bus address
D e v ice Address
Clock Generator ( 1101 001X
ICS-950810)
4 4
Title
Compal Electronics, Ltd.
Note List
Size Document Number Rev
CustomLA-1641 0.3
Date: Friday, November 29, 2002 Sheet 3 of 46
A B C D E
A B C D E
+CPU_CORE
AC10
AC12
AC14
AC16
AC18
AD11
AD13
AD15
AD17
AD19
AA10
AA12
AA14
AA16
AA18
AB11
AB13
AB15
AB17
AB19
AE10
AE12
AE14
AE16
AE18
AE20
AF11
AF13
AF15
AF17
AF19
AF21
AF2
AF5
AF7
AF9
C10
C12
C14
C16
C18
C20
D11
D13
D15
D17
D19
A10
A12
A14
A16
A18
A20
B11
B13
B15
B17
B19
E10
AC8
AD7
AD9
AA8
AB7
AB9
AE6
AE8
C8
D7
D9
A8
B7
B9
HA#[3..31] U40A HD#[0..63]
7 HA#[3..31] HD#[0..63] 7
VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
HA#3 K2 B21 HD#0
HA#4 K4 A#3 D#0 B22 HD#1
HA#5 L6 A#4 D#1 A23 HD#2
1
HA#6 K1 A#5 D#2 A25 HD#3
1
HA#7 L3 A#6 D#3 C21 HD#4
HA#8 M6 A#7 D#4 D22 HD#5
HA#9 L2 A#8 D#5 B24 HD#6
HA#10 M3 A#9 D#6 C23 HD#7
HA#11 M4 A#10 D#7 C24 HD#8
HA#12 N1 A#11 D#8 B25 HD#9
HA#13 M1 A#12 D#9 G22 HD#10
HA#14 N2 A#13 D#10 H21 HD#11
HA#15 N4 A#14 D#11 C26 HD#12
HA#16 N5 A#15 D#12 D23 HD#13
HA#17 T1 A#16 D#13 J21 HD#14
HA#18 R2 A#17 D#14 D25 HD#15
HA#19 P3 A#18 D#15 H22 HD#16
HA#20 P4 A#19 D#16 E24 HD#17
HA#21 R3 A#20 D#17 G23 HD#18
HA#22 T2 A#21 D#18 F23 HD#19
HA#23 U1 A#22 D#19 F24 HD#20
HA#24 P6 A#23 D#20 E25 HD#21
HA#25 U3 A#24 D#21 F26 HD#22
HA#26 T4 A#25 D#22 D26 HD#23
HA#27 V2 A#26 D#23 L21 HD#24
HA#28 R6 A#27 D#24 G26 HD#25
HA#29 W1 A#28 D#25 H24 HD#26
HA#30
HA#31
T5
U4
V3
A#29
A#30
A#31
Mobile D#26
D#27
D#28
M21
L22
J24
HD#27
HD#28
HD#29
W2 A#32 D#29 K23 HD#30
Y1 A#33 D#30 H25 HD#31
AB1 A#34 D#31 M23 HD#32
2
7 HREQ#[0..4] HREQ#[0..4]
HREQ#0 J1
A#35
NorthWood D#32
D#33
D#34
N22
P21
M24
HD#33
HD#34
HD#35
2
HREQ#1 K5 REQ#0 D#35 N23 HD#36
HREQ#2 J4 REQ#1 D#36 M26 HD#37
HREQ#3 J3 REQ#2 D#37 N26 HD#38
HREQ#4 H3 REQ#3 D#38 N25 HD#39
G1 REQ#4 D#39 R21 HD#40
7 H_ADS# ADS# D#40 P24 HD#41
D#41 R25 HD#42
AC1 D#42 R24 HD#43
+CPU_CORE V5 AP#0 D#43 T26 HD#44
R 9 1 C l o se to U37 pinM23 AP#1 D#44
AA3 T25 HD#45
R53 56_0402_5% AC3 BINIT# D#45 T22 HD#46
IERR# D#46 T23 HD#47
R91 220_0402_5% D#47 U26 HD#48
H6 D#48 U24 HD#49
7 H_BREQ0# D2 BR0# D#49 U23 HD#50
7 H_BPRI# G2 BPRI# D#50 V25 HD#51
7 H_BNR# BNR# D#51
G4 U21 HD#52
7 H_LOCK# LOCK# D#52 V22 HD#53
D#53 V24 HD#54
CLK_CPU_BCLK AF22 D#54 W26 HD#55
15 CLK_CPU_BCLK CLK_CPU_BCLK# AF23 BCLK0 D#55 Y26 HD#56
15 CLK_CPU_BCLK# BCLK1 D#56 W25 HD#57
D#57 Y23 HD#58
D#58 Y24 HD#59
F3 D#59 Y21 HD#60
7 H_HIT# E3 HIT# D#60 AA25 HD#61
7 H_HITM# HITM# D#61
E2 AA22 HD#62
7 H_DEFER# DEFER# D#62 AA24 HD#63
D#63
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_80
VCC_79
VCC_78
VCC_77
VCC_76
VCC_75
VCC_74
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
3 3
AC11
AC13
AC15
AC17
AC19
AC22
AC25
AD10
AD12
AD14
AD16
AD18
AD21
AD23
AA11
AA13
AA15
AA17
AA19
AA23
AA26
AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB24
H23
H26
A11
A13
A15
A17
A19
A21
A24
A26
E20
E18
E16
E14
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