Service Manuals, User Guides, Schematic Diagrams or docs for : TOSHIBA Toshiba L755D 21J Quanta BLF BLFD

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Toshiba L755D 21J Quanta BLF BLFD

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                1                                    2                                   3                                                         4                                                        5                           6                7                                                    8

               PCB STACK UP
                                                                                                           BLOCK DIAGRAM
                LAYER   1   :   TOP
                LAYER   2   :   GND
                LAYER   3   :   IN1
                LAYER   4   :   SGND1                                                                                                                            DP0/TXPN[0:1]                                  TRAVIS_L
                                                                                                                                                                                  DP0                                                       LVDS PANEL
A               LAYER   5   :   SGND2                                                                                                                                                                                                                                                                                                 A
                                                                                                                                                                 DP0_AUXP/N                                     ANX3110
                LAYER   6   :   IN2
                LAYER   7   :   VCC                  DDR3 1.5V support 1066~1333 MHz
                LAYER   8   :   BOT

                                                                                                                    DDR SYSTEM MEMORY
                                                            DDR III                          Dual Channel
                                                            SO-DIMM 0                                                                          Support 45W/35W TDP
                                                            SO-DIMM 1
                                                 Memory size MAX is 16GB per channel                                                        Socket FS1-LIano
                                                                                                                                            APU ( CPU + GPU )
                                                                                                     2.5GT/s                                                                      DP2
                                  PCIEx1                                                 PCI-Express Gen1                                    uPGA 722 pin                                                              HDMI CONN
                                                                                                                    GPP PCIEX1
              Atheros                                                                                                                                            DP2/PCI-E 0_3
              10/100M             GPP PCIE0                                              PCI-Express Gen1           GPP PCIEX1
               AR8158                                                                                2.5GT/s
    X'TAL                                                                                PCI-Express Gen1           GPP PCIEX1
                                                                                                                                                                                  PCI-Express Gen2
                                                                                                     2.5GT/s                                                 DP4_DP5/PCI-E 8_15                                            ATI GPU
                                               PCIEx1                                  PCIEx1                                                                                     PCIE X8
            Transformer                                                                                                                                UMI       DP1/TXPN[0:3]                                         Seymour XT S3
                                               GPP PCIE2                               GPP PCIE1
                                                                                                                  X4 UMI interface                                      DP1
B                                       Mini Card                             Mini Card                                                 2.5GT/s                                                                                                                                                                                       B

             RJ45                       WWAN/3G                               WiFi                                                                                                                                            X'TAL
                                                                                                                                                         UMI                                                                  27.0MHz

                                               USB 2.0                                        USB 2.0                                                               DP to VGA

                                                                  HDD (SATA)            SATA0           6Gbit/s
                                                                                                                    SATA Gen3
                                                                                                                                                                                                                           VGA CONN
                                SIM Card
                                                                                        SATA1           6Gbit/s
                                                                                                                    SATA Gen3
                                                                  ODD (SATA)
                                                                                                                    SATA Gen2
            USB 3.0/2.0 Combo X1                                                                   USB 3.0/2.0 USB3.0/2.0
                                                                                                                          Hudson-M2/M3                                                                X'TAL
                                                                                                                                                                         RTC                          32.768KHz
                                                                                                     USB 2.0        USB2.0

                                                                                                                                               FCBGA 656 pin            PCI-E
                                           USB 2.0
                    USB 2.0 DB
                     2 ports                                                                 Azalia ( HDA bus )     HDA                                                           RTC_CLK

                                                                                                                                                                                        32.768KHz sharing
C                                                                                                                                                                                                                                                                                                                                     C

                                           USB 2.0                                                                                       SPI                            LPC

                                           USB 2.0                                                                SPI ROM
                    CardReader                                                                                                                                        EC
                                                          Audio CODEC                                                                                               Nuvoton
                    RTS5138                                Conexant

                                  HP Jack       MIC Jack             SPK             DMIC            MDC                      SPI ROM                        Touch Pad            Keyboard                          Button on
                                                                                                                                                                                                                    mechanical key

D                                                                                                                                                                                                                                                                                                                                     D

                                                                                                                                                                                                                                                                                               Quanta Computer Inc.
                                                                                                                                                                                                                                                                                               PROJECT : BLF_BLFD
                                                                                                                                                                                                                                                             Size    Document Number                                            Rev
                                                                                                                                                                                                                                                                                       System Block Diagram                      1C

                                                                                                                                                                                                                                                             Date:   Tuesday, April 19, 2011          Sheet       1   of   53
                1                                    2                                   3                                                         4                                                        5                           6                7                                                    8
                  5                                        4                                                     3                                              2                                                              1

                                                               BLF/BLFD Power On Sequence: S5 > S0

D                                                                                                                                                                                                                                                                       D
                                    +VIN                                                                                                                            APU Power on sequence required:
                      +5VPCU/+3VPCU/+15V                                                                                                                            Llano APU:
                                                                      AC not present equal to LOW; AC present equal to High                                         1.Group A ( +1.5V_SUS, +2.5V_VDDA ) ramp before Group B
                                    ACIN                                                                                                                            ( +VDD_CORE, +VDDNB_CORE, +1.2V_VDDPR )
                                                                      Power button from switch to EC
                                                                      To turn on dual power rails
    S5+ NOT implemented
                          S5_ON/S5_CORE_EN                                                                                                                          1.+3V_S5 ramp before +1.1V_DUAL
    S5+ implemented       S5_CORE_EN                                  S5+ implemented to turn off dual power rails                                                  2.+3V ramp before +1.1V
                                                                                                                                                                    3.+3V_RTC must ramp at least 5 secs before the +3V_S5

                                                                                  20ms delay at least

                             RSMRST_GATE#                                                                                                                           Seymour XT S3 package Power-on sequence
                                                               50ms Max

                                 RTCLK                                                                                                                              All power rails reach nominal within 20ms
                                                                                  32ms Min                                                                          1 => +3V_GPU
                                                                                                Power button from EC to FCH                                         2 => +VGPU_CORE/+1V_GPU
                             PWR_BTN#_EC                                                                                                                            3 => +VGPU_CORE PWRGD to enable +1.5V_GPU
                                                                                                                                                                    4.=> +1V_GPU PWRGD to enable +1.8V_GPU                                                              C

                              SLP_S5#                                                                                                                                NOTE
                              SUS_ON                                                                                                                                1.+3V to turn on +3V_GPU

                                               +1.5V_SUS                                                                                                            2.+3V_GPU ready to enable +VGPU_CORE/+1V_GPU
                                                                                        +0.75V_DDR_VTT only will be shut down in S3 mode and for DDR3 SODIMM only
                                                                                                                                                                    ( +1V_GPU will ramp up before +VGPU_CORE )
               APU GROUP A power              +0.75V_DDR_VTT
                                                VDRAM_PWRGD                                                                                                         3.+VGPU_CORE PWRGD to enable          +1.5V_GPU
                                                SLP_S3#                                                                                                             3.+1V_GPU PWRGD to enable      +1.8V_GPU

                                                                                                                                                                    TRAVIS_L ANX3110 power on sequecne

                                                                                       Default controlled by +3.3V                                                  1.+3V must lead +1.2V_TRAVIS
                                                VDDA_PWRGD                                                                                                          2.+1.2V_TRAVIS must lead TRAVIS_RST#

                                               +VDDNB_CORE                                                                                                          NOTE: FCH must output PCIE_RST#_TRAVIS or
              APU GROUP B power                                                                                                                                     APU_PCIE_RST# after +1.2V_TRAVIS ready
B                                                                                                                                                                                                                                                                       B





                                                                                                        98ms < T <150ms

                                              FCH_PWRGD                                                 50ms Max


                                                                                               38ms Max
                                                                                                         101ms < T <113ms
                                              A_RST#(PLTRST#)                                                               75ns < T <100ns

A                                             PCIRST#                                                                           1ms < T <2.3ms                                                                                                                          A


                                                                                                                                                                                                                                    Quanta Computer Inc.
                                                                                                                                                                                                                                    PROJECT : BLF_BLFD
                                                                                                                                                                                                  Size    Document Number                                        Rev
                                                                                                                                                                                                                       POWER SEQUENCE
                                                                                                                                                                                                  Date:   Tuesday, April 19, 2011          Sheet   2   of   53
                  5                                        4                                                     3                                              2                                                              1
               5                                                                      4                                                               3                                                                 2                                             1

                                                      CPU core
                                                      NB core
                                                  (ISL6267HRZ-T)                           +VDDNB_CORE



                                                                                MAIND                                                 +5V                                 +5V_ODD
                                                                                                                   +5V                       AO3413
                                                                                          TPCA8030-H           +1.2V_VDDPR

                                                        5V/3V                   S5_ON                                                                                                  +3V
                                                                                                                   +3V_S5            +1.1V_DUAL                     +1.1V_DUAL                                         +1.1V
                                                      (PM6686TR)                          ME2306                                                                                                   AO4468


                                                                                                                   +3V      RUN_ON                                                                 VGA_PD                      FCH_VDDAN_33_DAC
                                                                                          AO6402A                                              G9661-25ADJF12U             +2.5V_VDDA        +3V             2N7002E

C                                                                                                                           +1V_GPU_PG                                                                                                                                                                                          C

                                                                                                                             +3VPCU               UP7706U8                  +1.8V_GPU


                                                                    +1.5V_SUS              2N7002K                                                        +VGPU_CORE_PG
                                                                                                                                                                                                      +1.5V_GPU     Suport 1.35V use
                                                                     MAIND                                                                            +5VPCU
                                                                    +1.5V_SUS              ME2306
                                                                                                                                                                                                       +1.5V_GPU    W/O 1.35V use
                                                       DDR PWR                                                                                        +1.5V_SUS

B                                                                                                                                                                                                                                                                                                                               B

                                                                    +1.5V_SUS                                                +0.75V_VREF_CA
                                                                                            Voltage Divider

                                                                    +1.5V_SUS                                                +0.75V_VREF_DQ
                                                                                            Voltage Divider


                                                            +3V_GPU              DGPU CORE/IO
                                                         +1.5V_GPU              (G9661-25ADJF12U)
                                            PX_MODE                                                                                                                                           +VGPU_CORE
                                                                                                                                 VGA_PD                                                                                                           +BIF_VDDC
                                                      DGPU CORE/IO                                                       +1.1V              2N7002E           +FCH_VDDAN_11_MLDAC
                                                                                          +VGPU_CORE                                                                                          +PCIE_VDDC
                                                  (ISL95870AHRUZ-T)                                                                                                                                                 DMN601K-7
A                                                                                                                                                                                                                                                                                                                               A


                                                                                                                                                                                                                                                                                            Quanta Computer Inc.
                                                                                                                                                                                                                                                                                            PROJECT : BLF_BLFD
                                                                                                                                                                                                                                                              Size    Document Number                                    Rev
                                                                                                                                                                                                                                                                      Power Tree
                                                                                                                                                                                                                                                              Date:   Tuesday, April 19, 2011      Sheet   3   of   53
               5                                                                      4                                                               3                                                                 2                                             1
    5                                     4                                                                               3                              2                                                  1

D                                                                                                                                                                                                                                      D

           B_SODIMM                               FS1 APU

                                                      100MHz (non-spread)
                                                                                                            INTERNAL CLOCK MODE


                                                                                                                                               100 MHz
                                                                                                                              SLT_GFX_CLKP/N                  Discrete GPU                                                             C

                                  33 MHz
                                              LPCCLK1                                                                                          100 MHz
                EC               32.768KHZ
                                                                                                                                 GPP_CLK1P/N                    WLAN
                                                                                                                                               100 MHz
                                                                                                                                                                LAN       (AR8158)

                                                                                                                                               100 MHz

                                   33 MHz                                                                                                      100 MHz
         LPC Debug port                       LPCCLK0                                                                                                        TRAVIS_L
                                                                                                          AMD HUDSON-M3
                                                                                                    Integrated CLOCK GENERATOR
B                              33 MHz                                                                                                                                                                                                  B
            SPI ROM                           SPI_CLK
                                 24 MHz
            HD AUDIO                          AZ_BITCLK
                                 48 MHz
        CARD READER                           14M_25M_48M_OSC

                                                                                  FOR MASTER                    FOR RTC

                                                                               25M HZ                         32.768K Hz
A                                                                                                                                                                                                                                      A

                                                                                                                                                                                                   Quanta Computer Inc.
                                                                                                                                                                                                   PROJECT : BLF_BLFD
                                                                                                                                                                   Size       Document Number                                   Rev
                                                                                                                                                                              Clock Distribution Diagram
                                                                                                                                                                   Date:     Tuesday, April 19, 2011      Sheet   4   of   53
    5                                     4                                                                               3                              2                                                  1
                     5                                          4                                                          3                                                          2                                                   1

D                                                                                                                                                                                                                                                                             D


                                                AA8                 PCI EXPRESS                    AA2   PEG_HDMI_TXDP2   C75    0.1U/10V_4X                             INT_HDMI_TXDP2
                                                      P_GFX_RXP0                      P_GFX_TXP0                                                                                            INT_HDMI_TXDP2 26

                                                AA9                                                AA3   PEG_HDMI_TXDN2                            C73    0.1U/10V_4X    INT_HDMI_TXDN2
                                                 Y7   P_GFX_RXN0                      P_GFX_TXN0   Y2                                                                                       INT_HDMI_TXDN2 26
                                                                                                         PEG_HDMI_TXDP1   C91    0.1U/10V_4X                             INT_HDMI_TXDP1
                                                 Y8   P_GFX_RXP1                      P_GFX_TXP1   Y1                                                                                       INT_HDMI_TXDP1 26
                                                                                                         PEG_HDMI_TXDN1                            C98    0.1U/10V_4X    INT_HDMI_TXDN1                                            P_GFX_TXP/N[3:0]
                                                      P_GFX_RXN1                      P_GFX_TXN1                                                                                            INT_HDMI_TXDN1 26
                                                 W5                                                Y4    PEG_HDMI_TXDP0   C86    0.1U/10V_4X                             INT_HDMI_TXDP0                                            correspond to DisplayPort 2.
                                                 W6   P_GFX_RXP2                      P_GFX_TXP2   Y5                                                                                       INT_HDMI_TXDP0 26
                                                                                                         PEG_HDMI_TXDN0                            C90    0.1U/10V_4X    INT_HDMI_TXDN0
                                                      P_GFX_RXN2                      P_GFX_TXN2                                                                                            INT_HDMI_TXDN0 26
                                                 W8                                                W2    PEG_HDMI_TXCP    C104   0.1U/10V_4X                             INT_HDMI_TXCP
                                                 W9   P_GFX_RXP3                      P_GFX_TXP3   W3                                                                                       INT_HDMI_TXCP 26
                                                                                                         PEG_HDMI_TXCN                             C110   0.1U/10V_4X    INT_HDMI_TXCN
                                                 V7   P_GFX_RXN3                      P_GFX_TXN3   V2                                                                                       INT_HDMI_TXCN 26
                                                 V8   P_GFX_RXP4                      P_GFX_TXP4   V1
                                                 U5   P_GFX_RXN4                      P_GFX_TXN4   V4
                                                 U6   P_GFX_RXP5                      P_GFX_TXP5   V5
                                                 U8   P_GFX_RXN5                      P_GFX_TXN5   U2
                                                 U9   P_GFX_RXP6                      P_GFX_TXP6   U3

                                                 T7   P_GFX_RXN6                      P_GFX_TXN6   T2
                                                 T8   P_GFX_RXP7                      P_GFX_TXP7   T1
                                PEG_RXP8         R5   P_GFX_RXN7                      P_GFX_TXN7   T4    PEG_TXP8_C       C652   DIS@0.1U/10V_4X                          PEG_TXP8
           17   PEG_RXP8                              P_GFX_RXP8                      P_GFX_TXP8                                                                                           PEG_TXP8 17
                                PEG_RXN8         R6                                                T5    PEG_TXN8_C                                C653   DIS@0.1U/10V_4X PEG_TXN8
           17   PEG_RXN8                              P_GFX_RXN8                      P_GFX_TXN8                                                                                           PEG_TXN8 17
                                PEG_RXP9         R8                                                R2    PEG_TXP9_C       C654   DIS@0.1U/10V_4X                          PEG_TXP9
           17   PEG_RXP9                              P_GFX_RXP9                      P_GFX_TXP9                                                                                           PEG_TXP9 17
           17   PEG_RXN9        PEG_RXN9         R9                                                R3    PEG_TXN9_C                                C655   DIS@0.1U/10V_4X PEG_TXN9         PEG_TXN9 17
C                                                     P_GFX_RXN9                      P_GFX_TXN9                                                                                                                                                                              C
                                PEG_RXP10        P7                                                P2    PEG_TXP10_C      C656   DIS@0.1U/10V_4X                          PEG_TXP10
           17   PEG_RXP10                             P_GFX_RXP10                    P_GFX_TXP10                                                                                           PEG_TXP10 17
           17   PEG_RXN10       PEG_RXN10        P8                                                P1    PEG_TXN10_C                               C658   DIS@0.1U/10V_4X PEG_TXN10        PEG_TXN10 17
                                PEG_RXP11        N5   P_GFX_RXN10                    P_GFX_TXN10   P4    PEG_TXP11_C      C657   DIS@0.1U/10V_4X                          PEG_TXP11
           17   PEG_RXP11                             P_GFX_RXP11                    P_GFX_TXP11                                                                                           PEG_TXP11 17
                                PEG_RXN11        N6                                                P5    PEG_TXN11_C                               C659   DIS@0.1U/10V_4X PEG_TXN11
           17   PEG_RXN11                             P_GFX_RXN11                    P_GFX_TXN11                                                                                           PEG_TXN11 17
           17   PEG_RXP12       PEG_RXP12        N8                                                N2    PEG_TXP12_C      C660   DIS@0.1U/10V_4X                          PEG_TXP12        PEG_TXP12 17
                                PEG_RXN12        N9   P_GFX_RXP12                    P_GFX_TXP12   N3    PEG_TXN12_C                               C661   DIS@0.1U/10V_4X PEG_TXN12
           17   PEG_RXN12                             P_GFX_RXN12                    P_GFX_TXN12                                                                                           PEG_TXN12 17
           17   PEG_RXP13       PEG_RXP13        M7                                                M2    PEG_TXP13_C      C662   DIS@0.1U/10V_4X                          PEG_TXP13        PEG_TXP13 17
                                PEG_RXN13        M8   P_GFX_RXP13                    P_GFX_TXP13   M1    PEG_TXN13_C                               C663   DIS@0.1U/10V_4X PEG_TXN13
           17   PEG_RXN13                             P_GFX_RXN13                    P_GFX_TXN13                                                                                           PEG_TXN13 17
                                PEG_RXP14        L5                                                M4    PEG_TXP14_C      C664   DIS@0.1U/10V_4X                          PEG_TXP14
           17   PEG_RXP14                             P_GFX_RXP14                    P_GFX_TXP14                                                                                           PEG_TXP14 17
           17   PEG_RXN14       PEG_RXN14        L6                                                M5    PEG_TXN14_C                               C665   DIS@0.1U/10V_4X PEG_TXN14        PEG_TXN14 17
                                PEG_RXP15        L8   P_GFX_RXN14                    P_GFX_TXN14   L2    PEG_TXP15_C      C666   DIS@0.1U/10V_4X                          PEG_TXP15
           17   PEG_RXP15                             P_GFX_RXP15                    P_GFX_TXP15                                                                                           PEG_TXP15 17
           17   PEG_RXN15       PEG_RXN15        L9                                                L3    PEG_TXN15_C                               C668   DIS@0.1U/10V_4X PEG_TXN15        PEG_TXN15 17
                                                      P_GFX_RXN15                    P_GFX_TXN15
                                                AC5                                                AD4    PCIE_TXP0_LAN_C C60    0.1U/10V_4X                             PCIE_TXP0_LAN
           35 PCIE_RXP0_LAN                           P_GPP_RXP0                     P_GPP_TXP0                                                                                            PCIE_TXP0_LAN 35
    LAN    35 PCIE_RXN0_LAN                     AC6                                                AD5    PCIE_TXN0_LAN_C                          C61    0.1U/10V_4X    PCIE_TXN0_LAN     PCIE_TXN0_LAN 35                 LAN
                                                AC8   P_GPP_RXN0                     P_GPP_TXN0    AC2    PCIE_TXP1_C     C71    0.1U/10V_4X                             PCIE_TXP1
             30   PCIE_RXP1                           P_GPP_RXP1                     P_GPP_TXP1                                                                                            PCIE_TXP1 30
    WLAN     30   PCIE_RXN1                     AC9                                                AC3    PCIE_TXN1_C                              C68    0.1U/10V_4X    PCIE_TXN1         PCIE_TXN1 30                     WLAN
                                                AB7   P_GPP_RXN1                     P_GPP_TXN1    AB2    PCIE_TXP2_C     C82    3G@0.1U/10V_4X                          PCIE_TXP2
             30   PCIE_RXP2                           P_GPP_RXP2                     P_GPP_TXP2                                                                                            PCIE_TXP2 30

    3G                                          AB8                                                AB1    PCIE_TXN2_C                              C83    3G@0.1U/10V_4X PCIE_TXN2                                          3G
             30   PCIE_RXN2                           P_GPP_RXN2                     P_GPP_TXN2                                                                                            PCIE_TXN2 30
                                                AA5                                                AB4                                 D3A
                                                AA6   P_GPP_RXP3                     P_GPP_TXP3    AB5
                                                      P_GPP_RXN3                     P_GPP_TXN3
                                                AF8                                                AF1    UMI_TXP0_C      C59    0.1U/10V_4X                             UMI_TXP0
             11   UMI_RXP0                            P_UMI_RXP0                      P_UMI_TXP0                                                                                           UMI_TXP0   11
B                                               AF7                                                AF2    UMI_TXN0_C                               C58    0.1U/10V_4X    UMI_TXN0                                                                                             B
             11   UMI_RXN0                            P_UMI_RXN0                      P_UMI_TXN0                                                                                           UMI_TXN0   11
             11   UMI_RXP1                      AE6                                                AF5    UMI_TXP1_C      C57    0.1U/10V_4X                             UMI_TXP1          UMI_TXP1   11
                                                AE5   P_UMI_RXP1                      P_UMI_TXP1   AF4    UMI_TXN1_C                               C56    0.1U/10V_4X    UMI_TXN1

             11   UMI_RXN1                            P_UMI_RXN1                      P_UMI_TXN1                                                                                           UMI_TXN1   11
             11   UMI_RXP2                      AE9                                                AE3    UMI_TXP2_C      C63    0.1U/10V_4X                             UMI_TXP2          UMI_TXP2   11
                                                AE8   P_UMI_RXP2                      P_UMI_TXP2   AE2    UMI_TXN2_C                               C62    0.1U/10V_4X    UMI_TXN2
             11   UMI_RXN2                            P_UMI_RXN2                      P_UMI_TXN2                                                                                           UMI_TXN2   11
                                                AD8                                                AD1    UMI_TXP3_C      C67    0.1U/10V_4X                             UMI_TXP3
             11   UMI_RXP3                            P_UMI_RXP3                      P_UMI_TXP3                                                                                           UMI_TXP3   11
             11   UMI_RXN3                      AD7                                                AD2    UMI_TXN3_C                               C64    0.1U/10V_4X    UMI_TXN3          UMI_TXN3   11
                                                      P_UMI_RXN3                      P_UMI_TXN3

                +1.2V_VDDPR   R65     196/F_6    K5                                                K4     P_ZVSS          R59      196/F_6
                                                      P_ZVDDP                             P_ZVSS

                                                      Llano APU

A                                                                                                                                                                                                                                                                             A

                                                                                                                                                                                                                        Quanta Computer Inc.
                                                                                                                                                                                                                        PROJECT : BLF_BLFD
                                                                                                                                                                                          Size    Document Number                                                      Rev
                                                                                                                                                                                                              Llano PCIE/UMI/GPP
                                                                                                                                                                                          Date:   Tuesday, April 19, 2011              Sheet        5      of     53
                     5                                          4                                                          3                                                          2                                                   1
                       5                                                                           4                                                                         3                                                                                  2                                                                             1

                                                                      U23A                                                                              M_A_DQ[0..63]   15                                                                                                 U23B
                                                                                                                                                                                                                                                                                                                                                          M_B_DQ[0..63]    16
                                                                                                                                                                                                        16 M_B_A[15:0]
            15 M_A_A[15:0]                                                       MEMORY CHANNEL A                                                                                                                                                                                     MEMORY CHANNEL B
                                                   M_A_A0       U20                                           E13     M_A_DQ0                                                                                                                      M_B_A0        T27                                              A14           M_B_DQ0
                                                   M_A_A1       R20   MA_ADD0                  MA_DATA0       J13     M_A_DQ1                                                                                                                      M_B_A1        P24       MB_ADD0                   MB_DATA0     B14           M_B_DQ1
                                                   M_A_A2       R21   MA_ADD1                  MA_DATA1       H15     M_A_DQ2                                                                                                                      M_B_A2        P25       MB_ADD1                   MB_DATA1     D16           M_B_DQ2
                                                   M_A_A3       P22   MA_ADD2                  MA_DATA2       J15     M_A_DQ3                                                                                                                      M_B_A3        N27       MB_ADD2                   MB_DATA2     E16           M_B_DQ3
D                                                  M_A_A4       P21   MA_ADD3                  MA_DATA3       H13     M_A_DQ4                                                                                                                      M_B_A4        N26       MB_ADD3                   MB_DATA3     B13           M_B_DQ4                                                D
                                                   M_A_A5       N24   MA_ADD4                  MA_DATA4       F13     M_A_DQ5                                                                                                                      M_B_A5        M28       MB_ADD4                   MB_DATA4     C13           M_B_DQ5
                                                   M_A_A6       N23   MA_ADD5                  MA_DATA5       F15     M_A_DQ6                                                                                                                      M_B_A6        M27       MB_ADD5                   MB_DATA5     B16           M_B_DQ6
                                                   M_A_A7       N20   MA_ADD6                  MA_DATA6       E15     M_A_DQ7                                                                                                                      M_B_A7        M24       MB_ADD6                   MB_DATA6     A16           M_B_DQ7
                                                   M_A_A8       N21   MA_ADD7                  MA_DATA7                                                                                                                                            M_B_A8        M25       MB_ADD7                   MB_DATA7
                                                   M_A_A9       M21   MA_ADD8                                 H17     M_A_DQ8                                                                                                                      M_B_A9         L26      MB_ADD8                                C1

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