Service Manuals, User Guides, Schematic Diagrams or docs for : TOSHIBA Toshiba Satellite Pro L40
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5 4 3 2 1
TERESA Block Diagram
FAN + SENSOR
ADM1032ARMZ
PAGE 4
CLOCK GEN
CPU ICS954310
D D
T2060 PAGE 5
4xx,5xx Series DISCHARGER
PAGE 2,3
CIRCUIT
PAGE 37
FSB Power On Sequence
533MHz PAGE 40
DC/BATT IN
LVDS & INV GMCH-M DDR2-533MHz Dual Channel DDR2 PAGE 41
PAGE 12
Calistoga SO-DIMM X 2 CPU VCORE
CRT 943GML
B0:02G010009121
PAGE 14,15,16 PAGE 50
PAGE 13
PAGE 6,7,8,9,10,11
C
SYSTEM PWR C
DMI Interface
T/P PAGE 51
BAT & CHARGER
PAGE 30
PAGE 57
PCIE *1 MINI CARD
KEYPAD WLAN
PAGE 26
MATRIX BTO
PAGE 29 LPC
EC IT8511E
INSTANT KEY
33MHz ICH7-M PCIE *1
NEW
Azalia
PAGE 38
PAGE 29,30 CARD
PCI PAGE 25 BTO
B0:02G010008811
33MHz
B LED Control PAGE
B
17,18,19,20
PAGE 30,38
USB 10/100 LAN
ISA SATA IDE RTL8100CL
PAGE 34,35
ROM
PAGE 24 PCMCIA
HDD CardBus PAGE 44 BTO
(SATA) R5C847
PAGE 43,44 BTO
MEDIA CARD SLOT
MIC PHONE JACK PAGE 28
PAGE 33 BTO
PAGE 23
USB 2.0
Azalia Codec CON X3
HEADPHONE JACK ODD
AD1986A PAGE 36
PAGE 22
PAGE 21,22,23 PAGE 28
A A
SPEAKER AUDIO AMP
PAGE 22 PAGE 22
MDC PCMCIA
PAGE 35
Title : BLOCK DIAGRAM
BTO
ASUSALPHATeK COMPUTER INC. Engineer: Horng Chou
Size Project Name Rev
Custom TERESA 1.1
Date: Tuesday, February 06, 2007 Sheet 1 of 57
5 4 3 2 1
http://laptop-motherboard-schematic.blogspot.com/
5 4 3 2 1
6 H_A#[16..3]
6 H_REQ#[4..0]
6 H_A#[31..17]
T202
H_D#[0..63] 6
1
D U201A D
H_A#3 J4 H1 H_ADS#
A[3]# ADS# H_ADS# 6
H_A#4 L4 E2 H_BNR# U201B
A[4]# BNR# H_BNR# 6
H_A#5 M3 G5 H_BPRI# H_D#0 E22 AA23 H_D#32
H_A#6 A[5]# BPRI# H_BPRI# 6 H_D#1 D[0]# D[32]# H_D#33
K5 F24 AB24
H_A#7 A[6]# H_DEFER# H_D#2 D[1]# D[33]# H_D#34
M1 H5 H_DEFER# 6 E26 V24
A[7]# DEFER# D[2]# D[34]#
ADDR GROUP 0
H_A#8 N2 F21 H_DRDY# H_D#3 H22 V26 H_D#35
A[8]# DRDY# H_DRDY# 6 D[3]# D[35]#
H_A#9 J1 E1 H_DBSY# H_D#4 F23 W25 H_D#36
DATA GRP 2
A[9]# DBSY# H_DBSY# 6 D[4]# D[36]#
DATA GRP 0
H_A#10 N3 H_D#5 G25 U23 H_D#37
H_A#11 A[10]# H_BR0# R201 H_D#6 D[5]# D[37]# H_D#38
P5 F1 H_BR0# 6 E25 U25
H_A#12 A[11]# BR0# 56Ohm H_D#7 D[6]# D[38]# H_D#39
P2 E23 U22
H_A#13 A[12]# H_IERR# H_D#8 D[7]# D[39]# H_D#40
L1 D20 1 2 K24 AB25
CONTROL
A[13]# IERR# +VCCP_AGTL+ D[8]# D[40]#
H_A#14 P4 B3 H_INIT# H_D#9 G24 W22 H_D#41
H_A#15 A[14]# INIT# H_INIT# 17 H_D#10 D[9]# D[41]# H_D#42
P1 J24 Y23
H_A#16 A[15]# H_LOCK# H_D#11 D[10]# D[42]# H_D#43
R1 H4 H_LOCK# 6 J23 AA26
H_ADSTB#0 A[16]# LOCK# H_D#12 D[11]# D[43]# H_D#44
6 H_ADSTB#0 L2 2 1 +VCCP_AGTL+ H26 Y26
ADSTB[0]# H_CPURST# H_D#13 D[12]# D[44]# H_D#45
B1 H_CPURST# 6 F26 Y22
1
H_REQ#0 RESET# H_RS#0 R202 H_D#14 D[13]# D[45]# H_D#46
K3 F3 H_RS#0 6 K22 AC26
H_REQ#1 REQ[0]# RS[0]# H_RS#1 Do Not Stuff
@ H_D#15 D[14]# D[46]# H_D#47
H2 F4 H_RS#1 6 H25 AA24
H_REQ#2 REQ[1]# RS[1]# H_RS#2 H_DSTBN#0 D[15]# D[47]# H_DSTBN#2
K2 G3 H_RS#2 6 T201 6 H_DSTBN#0 H23 W24 H_DSTBN#2 6
H_REQ#3 REQ[2]# RS[2]# H_TRDY# H_DSTBP#0 DSTBN[0]# DSTBN[2]# H_DSTBP#2
J3 G2 H_TRDY# 6 6 H_DSTBP#0 G22 Y25 H_DSTBP#2 6
H_REQ#4 REQ[3]# TRDY# H_DINV#0 DSTBP[0]# DSTBP[2]# H_DINV#2
L5 6 H_DINV#0 J26 V23 H_DINV#2 6
REQ[4]# H_HIT# DINV[0]# DINV[2]#
G6 H_HIT# 6
H_A#17 HIT# H_HITM#
Y2 E4 H_HITM# 6
H_A#18 A[17]# HITM# H_D#16 H_D#48
U5 N22 AC22
H_A#19 A[18]# H_D#17 D[16]# D[48]# H_D#49
R3 AD4 K25 AC23 Layout Note:
A[19]# BPM[0]# D[17]# D[49]#
ADDR GROUP 1
H_A#20 W6 AD3 H_D#18 P26 AB22 H_D#50 Comp0,2 connect with Z0=27.4 ohm,
A[20]# BPM[1]# D[18]# D[50]#
XDP/ITP SIGNALS
C H_A#21 U4 AD1 H_D#19 R23 AA21 H_D#51 C
H_A#22 Y5
A[21]# BPM[2]#
AC4 +VCCP_AGTL+ H_D#20 L25
D[19]# D[51]#
AB21 H_D#52 make trace length shorter than 0.5".
A[22]# BPM[3]# D[20]# D[52]# Comp1,3 connect with Z0=54.9 ohm,
DATA GRP 1
H_A#23 U2 AC2 PRDY# 1 T203 H_D#21 L22 AC25 H_D#53
DATA GRP 3
H_A#24 A[23]# PRDY# H_PREQ# 1 R203 Do Not @
Stuff H_D#22 D[21]# D[53]# H_D#54
R4 AC1 2 L23 AD20 make trace length shorter than 0.5".
H_A#25 A[24]# PREQ# H_TCK R204 56Ohm H_D#23 D[22]# D[54]# H_D#55
T5 AC5 1 2 M23 AE22 Comp[3:0] at least 25 mils away from
H_A#26 A[25]# TCK H_TDI R205 56Ohm H_D#24 D[23]# D[55]# H_D#56
T3 AA6 1 2 P25 AF23
H_A#27 A[26]# TDI H_TDO R206 Stuff
Do Not @ H_D#25 D[24]# D[56]# H_D#57 any other toggling signal.
W3 AB3 1 2 P22 AD24
H_A#28 A[27]# TDO H_TMS R207 56Ohm GND H_D#26 D[25]# D[57]# H_D#58 27.4 ohm connects with an ~18mil
W5 AB5 1 2 P23 AE21
H_A#29 A[28]# TMS H_TRST# 1 H_D#27 D[26]# D[58]# H_D#59
Y4 AB6 R208 2 56Ohm T24 AD21 wide trace to comp0.
H_A#30 A[29]# TRST# CPU_DBR# T204 +VCCP_AGTL+ H_D#28 D[27]# D[59]# H_D#60
W2 C20 1 R24 AE25 54.9 ohm connect with 5mil-wide
H_A#31 A[30]# DBR# Do Not Stuff H_D#29 D[28]# D[60]# H_D#61
Y1 L26 AF25 to comp1
H_ADSTB#1 A[31]# H_PROCHOT_S# H_D#30 D[29]# D[61]# H_D#62
6 H_ADSTB#1 V4 D21 T25 AF22
2
ADSTB[1]# PROCHOT# CPU_THRM_DA H_D#31 D[30]# D[62]# H_D#63
A24 CPU_THRM_DA 4 N24 AF26
THERMDA D[31]# D[63]#
THERM
H_A20M# A6 A25 CPU_THRM_DC R209 H_DSTBN#1 M24 AD23 H_DSTBN#3
17 H_A20M# A20M# THERMDC CPU_THRM_DC 4 6 H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 6
H_FERR# A5 1KOhm H_DSTBP#1 N25 AE24 H_DSTBP#3
17 H_FERR# FERR# 6 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 6
H_IGNNE# C4 C7 PM_THRMTRIP# 1% H_DINV#1 M26 AC20 H_DINV#3
17 H_IGNNE# IGNNE# THERMTRIP# PM_THRMTRIP# 4,17 6 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 6
1
H_STPCLK# D5 GTL_REF AD26 R26 H_COMP0 R210 1 2 27.4Ohm 1%
17 H_STPCLK# STPCLK# GTLREF COMP[0]
H_INTR C6 <500 mil (55 Ohm) MISC U26 H_COMP1 R211 1 2 54.9Ohm 1% GND
HCLK
17 H_INTR
2
H_NMI LINT0 CLK_CPU_BCLK COMP[1] H_COMP2 R212 27.4Ohm 1%
B4 A22 U1 1 2
17 H_NMI CLK_CPU_BCLK 5 T/B trace 5
1
H_SMI# LINT1 BCLK[0] CLK_CPU_BCLK# C201 R213 @R214 1
@ R214 TEST1 COMP[2] H_COMP3 R215 54.9Ohm 1%
17 H_SMI# A3 A21 CLK_CPU_BCLK# 5 2 C26 V1 1 2
SMI# BCLK[1] Do Not Stuff 2KOhm Space 25 Do Not Stuff TEST1 COMP[3]
AA1 @ 1% R216 1 2 TEST2 D25 E5 H_DPRSTP#
2
RSVD[1] TEST2 DPRSTP# H_DPRSTP# 17,50
AA4 T22 51Ohm B5 H_DPSLP#
1
RSVD[2] RSVD[12] DPSLP# H_DPSLP# 17
AB2 A2 GND D24 H_DPWR#
RSVD[3] RSVD[A2] DPWR# H_DPWR# 6
AA3 CPU_BSEL0 B22 D6 H_PWRGD
RSVD[4] 5 CPU_BSEL0 CPU_BSEL1 BSEL[0] PWRGOOD H_PWRGD 17
M4 D2 GND GND B23 D7 1
RESERVED
RSVD[5] RSVD[13] 5 CPU_BSEL1 CPU_BSEL2 BSEL[1] SLP#
B N5 F6 C21 AE6 T205 B
RSVD[6] RSVD[14] 5 CPU_BSEL2 BSEL[2] PSI#
T2 D3 H_CPUSLP#
RSVD[7] RSVD[15] PM_PSI# H_CPUSLP# 6,17
V3
RSVD[8] RSVD[16]
C1 For Celeron M PM_PSI# 50
B2
RSVD[9] RSVD[17]
AF1 (070122)Change CPU Socket
C3 D22 into PN=12G011204796
RSVD[10] RSVD[18]
RSVD[19]
C23 BCLK
B25
RSVD[11] RSVD[20]
C24 FSB BSEL2BSEL1BSEL0
133MHz 533MHz L L H
(070122)Change CPU Socket
into PN=12G011204796
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