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Maintenance - 275412754P Service Vol. 1
MICROCOMPUTER SYSTEM MAINTENANCE
Several maintenance aids are built into the micro- "ROM XX TESTS BAD. PUSH A BUTTON TO CONT."
computer system. These operating tests demonstrate
correct performance or indicate the location of a prob- "ROM XX MISPLACED. PUSH A BUTTON TO CONT."
lem, if any.
The switch settings that set up two of these tests "TIMER TESTS BAD. PUSH A BUTTON TO CONT."
are described first. These are followed by descriptions Cross-reference tables between the ROM and RAM
of the three tests. numbers given in error messages (XX) and the circuit
numbers of the parts are given in Table 6-8 and Table
In the first test, the microcomputer executes a self-
test that verifies, as much as possible, correct opera-
6-9.
tion. RAM, ROM, and interface adapters are checked. If the entire test is successful, the instrument initial-
Any failure found is indicated by LEDs on the GPlB izes and begins normal operation.
board.
The second test forces the microcomputer to cycle
through all of its addresses. This test requires less of
the system to run than does the first test, so it may be
used to troubleshoot problems that disable the first test
mode. Microcomputer System Test
The third test exercises the instrument bus to iso- The microcomputer system test is chosen by setting
late problems in data transfer between the microcom- switch 8 of S1050 closed and switch 7 of S1050 open.
puter and the instrument. The microcomputer reports the test results via the LEDs
on the GPlB board rather than on the CRT, allowing this
test to be performed when the display is inoperative. If
a problem is found, the test stops and the problem is
indicated by one of the LEDs on the GPlB board. If no
problem is found, the system test takes two minutes.
Memory Board Option Switch
The system test does not begin normal operation
S1050 on the Memory board selects the microcom- after the test is complete.
puter system test modes, as well as selecting some
instrument options. Figure 6-26 shows the selections
Addresses are specified as hexadecimal numbers in
controlled by the individual switches of S1050.
this description.
The microcomputer reads these switches only at
power-up. Any change in a switch position takes effect, 1. The microcomputer first verifies the check sum
when the instrument is next powered up. of the system ROM portion of U3050 on the Memory
board. The check sum test uses no memory except for
U3050. The correct ROM must be installed, the clock
on the Processor board must be present, and the
microcomputer system bus must be operating correctly.
Power-up Self Test If the correct check sum is not obtained, the routine
halts and lights DS1047 on the GPlB board. If the test
Normal instrument operation is selected by setting stops but does not light DS1047, and everything else
both switch 7 and switch 8 of S1050 closed. At power- seems to be in order, the Address Bus Test (described
up, the processor executes steps 1 and 2, the first part later in this section) should be performed.
of step 3, and steps 4 and 5 of the Microcomputer Sys-
tem Test described below. If the first two steps in the 2. The microcomputer next checks part of the pro-
test are successful, any problems in the other three cessor interface to the instrument bus PIA, U1010, on
steps are reported on the crt. Possible error messages the Processor board. If the test fails, the routine stops
are: and lights DS1050 on the GPlB board. If the test
succeeds, the processor assumes that the instrument
bus interface is working, and displays "PROCESSOR
"RAM XX TESTS BAD. PUSH A BUTTON TO CONT." SYSTEM TEST, PLEASE WAIT." on the crt.
Maintenance - 275412754P Service Vol. 1
OPEN (1) CAUSES INSTRUMENT TO REPORT SETTINGS (NO WAVEFORMS) IN TALK ONLY M D .
OE
CLOSED (0) CAUSES INSTRUMENT TO REPORT BOTH SETTINGS AND WAVEFORMS IN TALK ONLY M D .
OE
W = NORMAL OPERATION OPEN (1) ENABLES POWER-ON SRQ
01 = POWER-UP SELF TEST CLOSED (0) DISABLES POWER-ON SRQ
10 = NOT DEFINED
11 = INSTRUMENT BUS CHECK
ISED
CLOSED
OFF (open) =
-- - -
Figure 6-26. Options switch on the Memory board.
3. The microcomputer next checks RAM. The RAM Table 6-8
test contains three ~ a r t s The first art ~erforms auick
. a R A M TEST
test of all volatile' RAM ( ~ 1 0 1 0 and U3020 on' the
' RAM RAM DS1048
Memory Board). The microcomputer loads the bit pat- Number Socket Pulses
tern 01010101 into a RAM location, reads the location,
and compares what is returned to what was stored.
The microcomputer then repeats this test with the pat-
tern 10101010. This step does not rely on the RAM
being good to execute.
If a reading error occurs, the microcomputer stops
the test and pulses LED DS1048 on the GPlB board the
number of times corresponding to the RAM that failed
the test (refer to Table 6-8). The third part of the test is similar to the first part.
However, the memory contents are allowed to reside in
The second part of the test is a Moving Inversions memory for thirty seconds before being read back. The
test of all RAM (volatile and non-volatile). This test results are reported via DS1048.
assumes that a few byes of the RAM are good. If a
RAM fails this test, DS1048 on the Memory board is
pulsed as described earlier.
Maintenance - 275412754P Servlce Vol. 1
4. The microcomputer next check sums all ROMs. 6. The microcomputer resets the GPIA, U2050, on
The check sum stored in each ROM is compared to the the GPlB board and checks to see that the GPlA is not
check sum formed by the successive 16-bit spiral sum addressed to talk or listen. The GPlA is set t o the
of each byte in the ROM, starting at the third location in listen-only mode and checked t o see that it is
the ROM. The ROM number coded into each ROM will addressed to listen. The GPIA is then set to the talk-
cause an error if a ROM is installed in the wrong loca- only mode and checked to see that it is addressed to
tion. talk. If any part of this step fails, the test stops and LED
DS1052 on the GPlB board is lit.
The Tektronix part number is also coded into each
ROM. If the part number suffix and its complement,
which are stored in the fifth and sixth bytes of the ROM
header, do not read as complements, the microcom-
puter assumes that no ROM is installed and does not If all steps in the test are successfully completed,
attempt the checksum test. the microcomputer lights LED DS1054 on the GPlB
board. The LED is lit continuously if no empty ROM
If a bad or misplaced ROM is found, the microcom-
sockets are found, or pulsed the number of times
puter pulses DS1049 on the GPlB board N+l times,
corresponding to the number of empty ROM sockets
where N is the number of the ROM in error (e.g., a bad
found. If the number of pulses is greater than the
ROM #3 will cause four pulses; refer to Table 6-9).
number of absent ROMs, a ROM (or ROMs) was
Missing ROMs are reported as described in part 6.
missed in step 4. Look for a problem on the chip-select
line or on the "D7" data bus line.
If the microcomputer system passes the test, but
does not control the instrument, run the Instrument Bus
ROM
Number
- ROM
Socket
Table 6-9
R n TEST
C
Board
DS1049
Pulses
Check described later in this section.
0 U3060 A54 Memory 1 Address Bus Test
1 U3060 A56 Memory 2 Select the address bus test by moving jumper
2 u1010 A56 GPlB 3 P3015 on the Processor board to the TEST position.
3 U1010 A56 GPlB 4 This forces the 6808's data lines to hexadecimal 5F. As
4 U1020 A56 GPlB 5 a result, the 6808 continuously executes a "CLR B"
5 u1020 A56 GPlB 6 instruction, and repetitively cycles through all of its
6 U1025 A56 GPlB 7 address space. There should be a known pattern on
7 U1025 A56 GPlB 8 the microcomputer address and control lines and at the
8 UlO35 A56 GPlB 9 output of the address decoders. This allows qualified
9 UlO35 A56 GPlB 10 service personnel to correct problems that prevent the
10 U3Ol5 A56 GPlB 11 microcomputer from running its self-test.
11 U3Oi 5 A56 GPlB 12
12 U3020a A56 GPlB 13 The spectrum analyzer will not function while run-
13 U3020a A56 GPlB 14 ning this test.
14 U3030a A56 GPIB 15
15 U3030a A56 GPlB 16
16
17
- U3050
U3050
A54
A54
Memory
Memory
17
18 Microcomputer Bus - As the microcomputer
cycles through its address space, it toggles the address
lines. The MSB, A15, has a period of approximately
1540 ms. Each line, A14 through AO, has a period half
that of the previous line. Thus, the LSB A0 has a period
of approximately 4.7 ps. High-order lines A15 through
5. The microcomputer next tests U2015, a timer chip A12 are shown in Figure 6-27. Ignore the narrow pulses
on the Processor board. If any of the timers in U2015 that may be evident during the low portion of each
result in time delays that are too short or too long, the cycle.
test stops with LED DS1053 on the GPlB board lit.
a These chips ere loaded on the GPlB board only when certain
options are installed in the instrumenet.
Maintenance - 275412754P Service Vol. 1
-
OXXX
-
CXXX
Figure 6-27. A15 through A12 in microcomputer test mode. Figure 6-28. Four main block select outputs of address
decoder U2045.
The data lines on the microprocessor side of U2025
on the Processor board are static; D7 and D5 are low,
the others are high. The TEST position of P3015 dis-
ables U2025. On the bus side of this buffer, the data
lines are driven by the various memory devices on the
bus as they are addressed.
Examining the data lines can locate shorted or open
lines; i.e., lines inactive at high, low, or in-between
states or changing in unison, usually to indeterminate
logic levels of +I to +2 V. A problem related to a par-
V
ticular device may be evident only while that device is
addressed.
U3040
PIN 9
Memory Address Decoders - Address decoder
U2045 on the Memory board sets its outputs low in turn
to access blocks of memory space. The four main
block-select outputs are shown in Figure 6-28.
U3025 on the Memory board decodes the RAM
addresses. Because of the power-up condition of the
bank select, only one of the non-volatile RAM chips will
be selected. The RAM select outputs and their relation-
ship to Oxxx(bar) is shown in Figure 6-29.
U3040 and U3045 on the Memory board decode the
select line and the select line for S1050. These sig- Figure 6-29. RAM select output in relation to OXXX.
nals are shown in Figure 6-30.
Ignore the narrow pulses evident during the time
each output is asserted. The pulses result from address
lines toggling between microcomputer cycles.
Maintenance - 275412754P Service Vol. 1
Processor Address Decoder - Address decoder in Figure 6-32.
U3035 on the Processor board decodes several chip-
selects. YO, Y1, Y5, and Y7 are shown in relation to the
line in Figure 6-31.
Clocks and Control Lines - The 6808 clock input
line should be a square wave with a period of approxi-
mately 0.293 ps, The 4 2 output on pin 37 should have
a period of approximately 1.17 ps. VMA, RESET, NMI,
and R/W should be high. IRQ(bar) may be either high
or low, depending on how assemblies on the instrument
bus power up.
OPTIONS
-1 SWITCH
u SELECT
Figure 6-30.176 and S1050 select lines in relation to OXXX.
Figure 6-32. Chip selects Y2, Y4, and Y6 in relation t o 7 .
Instrument B u s T e s t
If the microcomputer performs the power-up self-
test, but fails to properly control the instrument, the
instrument bus interface may be faulty. Select the
instrument bus test by setting the option switch as
shown in Figure 6-26. The microcomputer continuously
writes to the instrument bus in a repetitive manner, so
the instrument does not operate normally.
The pattern on the instrument bus toggles DATA
VALID and POLL and exercises the address and data
lines. The address lines change when DATA VALID is
low and the data lines change when DATA VALID is
high. However, if an assembly on the bus is requesting
Figure 6-31. Chip selects YO, Y1, Y5, and Y7 in relation to service because of the way it powered up, DBO-DB4
176. may continue to change after DATA VALID goes low. In
this case, an assembly or assemblies may respond to
the high state of POLL and the changing state of AB7
GPlB Board Address Decoders -
Address and attempt to report status.
decoder U1055 on the GPlB board sets its outputs low
to select the GPIA, the GPlB address switch and the
bank latch. Y2, Y4, and Y6 are shown in relation t o m
Maintenance - 275412754P Service Vol. 1
The pattern for the upper address and data lines is TROUBLESHOOT1NG ON THE
shown in Figure 6-33. From address or data line 7 to
line 0, each line changes at twice the rate of the previ-
INSTRUMENT BUS
ous line, resulting in 128 cycles on the LSB lines. The
initial pulse on the upper four data lines is not part of
the +2 pattern and is not repeated on the lower four lnstrument Bus Data Transfers
data lines. It is possible to discover open or shorted There are two commands and queries provided to
lines by comparing the patterns to those in Figure 6-33, aid troubleshooting of circuit functions controlled by the
checking that they divide by 2. Look for lines that stay instrument bus. These circuits get data from the micro-
high or low, change together or at wrong times in the computer or respond with data for the microcomputer.
pattern, or go to indeterminate logic levels (1 V to 2 V). The ADDR command and ADDR query set and return
the instrument bus address for the DATA command.
The DATA command and DATA query set and return
data on the instrument bus.
CAUTION
Because the DATA command changes the
status of internal hardware, its use may
prevent normal Spectrum Analyzer opera-
tion, Incorrect settings of some hardware
could cause instrument damage.
These commands and queries are transmitted to the
Spectrum Analyzer with the PRINT statement. The
spectrum analyzer response to a query is input into a
string variable with the INPUT statement. A string vari-
able is formed by ending the variable name with a dollar
sign ($). Examples: A$, X I $.
For the GPlB PRIMARY ADDRESS, enter the
decimal equivalent of the spectrum analyzer rear-panel
GPlB ADDRESS switch settings.
A. DATA VALID, POLL and the upper two address lines ADDR (instrument bus address) command
A67 and AB6.
sv
DATA VALID
-+. . .', .- .' . HEX DlGlT - A character in the sequence 0
through 9 and A through F that represents a hexade-
POLL cimal digit. The two digits (in order) form a number to
f
represent a location on the instrument bus used by fol-
lowing DATA commands. If a character is not a hexa-
decimal digit or part of a pair of digits, it is not used to
execute the ADDR command, and an error is reported.
I 6. DATA VALID. POLL and the upper two data valid lines
0 6 7 and DB6. 441 6-94A
ADDR (instrument bus address) query
Figure 6-33. Instrument bus check.
Maintenance - 275412754P Service Vol. 1
Response to ADDR query Errors related to these commands are 41, invalid
DATA or ADDR argument contents, and 42, DATA
direction not compatible with ADDR direction.
HEX DIGIT HEX DIGIT
DATA (instrument bus data) command
Instrument Bus Registers
Registers provide the link between the instrument
bus and microcomputer controlled functions. The regis-
ters are defined here in the same order as they appear
in the Diagrams section. The definitions are provided to
help in constructing DATA commands and interpreting
responses to DATA queries.
The data is presented here as binary. In some cases
a data value occupies the entire register width; for
HEX DIGITS - As with ADDR, a pair of digits forms
instance, a value in digital storage. In other cases, a
a hexadecimal number. The number is a data value to
single bit or group of bits in the register forms a code;
be sent on the instrument bus to the location specified
for instance, the upper five bits in the sweep rate and
by the last ADDR command. This allows internal spec-
mode register indicate the sweep timeldivision. The
trum analyzer parameters to be set for service; these
meaning of the data is not fully defined here; refer to
parameters control functions by setting the status or
the description of the circuit module in Section 5 for
mode of spectrum analyzer circuit assemblies. Up to 16
details.
pairs of characters are accepted. If a character is not a
hexadecimal digit or part of a pair of digits, the data To use the binary codes presented here with the
byte formed by the pair is not executed and an error is DATA command and query statements, you must con-
reported. Also, an error is reported when data is sent to vert binary to hexadecimal. The binary code number
an invalid address. 0100101 1 is used as an example in the following steps.
1. Group the lower four bits and the upper four bits
(break the data byte in half).
DATA (instrument bus data) query 01001011 - 0100 1011
2. Convert each group of four bits to a hexadecimal
digit. Hexadecimal digits range from 0 to F in the
sequence 0123456789ABCDEF.
0100
1011
-
- 4
B (i.e., 8+0+2+1-11, which is hexadecimal B)
Response to DATA query 3. Group the two hexadecimal digits together, keep-
ing their respective places.
4 and B make the two-digit hexadecimal number 4 8
The information in Table 6-10 is separated by regis-
ters. The following information is related to the table
information by leading alpha designators.
Combined ADDR command and DATA command
A. Variable Resolution (refer to diagram 20)
DATA COMMAND The microcomputer writes to two variable resolution
registers. The data MSB steers the other bits that are
defined into the desired register. When DB7 equals 1, it
steers DBO through DB2 to select the resolution
bandwidth. When DB7 equals 0, it steers DB6 through
DBO to select the amount of gain added in the VR sec-
tion and the band leveling gain (gain adjustment related
The address command may precede a data com- to front-end response in each band). These two func-
mand or query to identify the instrument bus location as tions are addressed and set together by the same data
part of the same message. byte.
Maintenance - 275412754P Service Vol. 1
B. Log and Video Amplifier (refer to diagram 23) I. 1st LO Driver (refer to diagram 33)
There are two registers that receive data from the Register 72 controls functions on the 1st LO Driver
microcomputer. One register controls video offset (78) board. Register 7E is added to make the PEAKing con-
and the other controls the display modes and the verti- trot programmable.
cal scale factor (79).
J. Preselector Driver (refer to diagram 34)
C. Video Processor (refer to diagram 24)
Reaister 77 controls functions on the Preselector
Register 7C controls out-of-band clamping, video river.- he single bit DB3 responds on the data bus to
filtering, and leveling. indicate that the board is installed when the microcom-
puter performs a read at F7.
D. Digital Storage, Vertical (refer to diagram 25)
K. CENTERIMKR FREQUENCY Control (refer to
Registers 7A and FA on the Vertical Digital Storage
board transfer display data to and from the microcom- diagram 35)
puter for spectrum analyzer GPIB operations. Register Register 70 is provided for control functions and
7B controls digital storage functions. register 71 is provided for data values for center fre-
quency DAC(s). A read, FO, returns the results of a
comparison of the DAC output voltage and a memory
voltage.
E. 2-Axis & RF lnterface (refer to digram 28)
Register 4F on the Z-Axis & RF lnterface board
enables Z-axis and RF attenuator control. Register CF
reports power supply status. L. Auxiliary Synthesizer Control (refer to diagram
37)
Register 7D accepts data to set the synthesizer
chip, U4041, to output 200 MHz t o 220 MHz in 400 kHz
steps. Values of R, A, and N are given to determine the
F. Crt Readout (refer to diagram 30) output frequency as given by the formula
Register 5F controls crt readout and data steering.
Register 2F accepts data from the microcomputer.
where R, the reference division ratio, is set at 5 and P
is the prescale value of 32. N values needed are 31
through 34, while A ranges from 0 to 31. (Table 6-11
shows the fout results for given N and A values.)
G. Sweep (refer to diagram 31)
The microcomputer writes to registers O and 1F to
F
control sweep rate, mode, holdoff, interrupts, and
triggering.
M. Phase Lock (refer to diagram 39)
Register 73 accepts data t o preload the divide-by-n
counter and control the synthesizer. Successive reads
from register F3 obtain status and counter outputs.
H. Span Attenuator (refer to diagram 32) After resetting the counter output register selector,
three read cycles return status bits and counter bits in
Registers 75 and 76 control the span attenuator. the most significant byte and remaining counter bits in
following bytes.
Maintenance - 2754/2754P Service Vol. 1
N. Front Panel (refer to diagram 43) Table 6-10 (contl
Reading from F4 accesses the keyboard encoder
and the CENTERIMKR FREQUENCY control encoder. I Description
-
Out-of-band clamp no
Table 6-10
INSTRUMENT BUS REGISTERS
clamp
-
Out-of-band clamp clamp
r Data Bits
7 6 5 4 3 2 1 0
A. Variable
I Description
upper 5 div
Out-of-band clamp = clamp
lower div
-
Out-of-band clamp clamp
Resolution (3F) lower 5 div
Resolution Bandwidth Video filter off
Video filter 30 kHz
1 x x x x 0 0 1 1 MHz Resolution Bandwidth Video filter 3 kHz
1 x x x x 0 1 0 100 kHz Resolution Bandwidth Video filter 300 Hz
1 x x x x 0 1 1 10 kHz Resolution Bandwidth Video filter 30 Hz
1 x x x x 1 0 0 1 kHz Resolution Bandwidth Video filter 3 Hz
l x x x x l O l 100 Hz Resolution Bandwidth Video filter 0.3 Hz
Gain, Leveling Base-line leveling on
Base-line leveling off
0 0 0 0 0 x x x Band 1 Leveling
0 0 1 0 0 x x x Band 2 Leveling
0 0 0 1 O x x x Band 3 Leveling Horizontal Digital Storage
0 0 1 1 o x x x Band 4 Leveling Board
0 0 0 0 1 x x x Band 5 Leveling
0 0 1 0 1 x x x Band 6 Leveling
0 0 0 1 l x x x Band 7 Leveling Digital Storage Acquisition
0 0 1 1 1 x x x Band 8 Leveling Enable
0 1 0 0 0 x x x Band 9 Leveling Digital Storage Acquisition
0 1 1 0 0 x x x Band 10 Leveling Disable
o x x x x o o o 0 dB Gain Extended Address 2
0 x x x x 0 0 1 10 dB Gain Extended Address 1
o x x x x 1 0 0 20 dB Gain Extended Address 0
0 x x x x 1 0 1 30 dB Gain B-SAVE A on
O x x x x l l l 40 dB Gain B-SAVE A off
B. Log & Video VlEW B on
Amplifier VlEW B off
VlEW A on
Video Offset (78)
DB7-DBO - -
LSB 114 dB
Total range 63.75 dB
VlEW A off
SAVE A on
SAVE A off
Modes and Scale Factor (79) Subaddress bits for Port 7A
giving subaddresses 7-0.
l x x x x x x x Pulse stretcher on Addressing 7A.6 transfers
o x x x x x x x Pulse stretcher off the bus to the Vertical Digi-
X l X X X X X X ldentify offset on tal Storage board.
x 0 x x x x x x ldentify offset off
x x 0 1 x x x x Lin
x x l o x x x x Log Secondary Marker position
x x 0 0 x x x x Full-screen deflection bits
DB3-DBO Log vertical scale factor in Secondary Marker trace bit
dBldiv
Maintenance - 2754/2754P Service Vol. 1
Table 6-10 (cont) e 6-90 (cont)
Data Bits Data Bits
7 6 5 4 3 2 1 0 Description 7 6 5 4 3 2 1 0 Description
D. Digital Storage (cont) D. Digital Storage
(cont)
Horizontal Digital
Storage Board (cont) Horizontal Digital Storage
Board (cont)
Secondary Marker
position bi;s Digital Storage position bits
Secondary Marker
trace bit
Always low to indicate that it
is from the Horizontal Digital
DBI-7 Primary Marker posi- Storage board
tion bits
DBO & DB1 Digital Storage position bits
DBO Primary Marker trace
bit Vertical Digital Storage Board
Primary Marker posi- Data values from digital
tion bits storage. A write to 7B initial-
Primary Marker trace izes output to begin at the left
bit of the trace and proceed to
the right
Digital Storage
address bits Always high to indicate that it
is from the Vertical Digital
Storage board
Transfers the bus to
the Vertical Digital
Storage board. Data values for digital storage.
A write to 7 8 clears the
Determines if bus address counter so values are
transfer is for a single stored for points on the
cycle or until it is display starting at the left and
returned by the Verti- proceeding to the right in
cal Digital Storage order
board.
Disable Update Marker
x l l x x x x x PeaklAverage cursor in knob
Loading ADDR7-0 position
reloads the last X I o x x x x x PeakIAverage cursor in Peak
ADDR9,8 position
x 0 1 x x x x x PeakIAverage cursor in Aver-
age position
Primary Marker inten- x x x l x x x x Max Hold on
sity bits x x x o x x x x Max Hold off
Secondary Marker
intensity bits
Maintenance - 2754/2754P Service Vol. 1
Tab 6-10 Icontl Table i-10 Icontl
Data Bits Data Bits
7 6 5 4 3 2 1 0 Description 7 6 5 4 3 2 1 0 Description
E. Z-Axis & RF F. Crt Readout
Interface (cont)
Z-Axis & RF Attenuator
1 x x x x x x x
(4F)
Baseline clipper on
If DB1 in 5F -1 - A7,
A6 of address. With A8
O x x x x x x x Baseline clipper off and A9 in 5F, they specify
x l x x x l x l
X l X X X l X O
x o x x x l x l
0 dB RF attenuation
10 dB RF attenuation
20 dB RF attenuation
the line number (0-F).
If DB1 in 5F
A5-A0 of address. This
-
1 -
X l X X X O X l 30 dB RF attenuation specifies the character
x
x
1
o
x
x
x
x
x
x
o
o
x
x
o
1
40 dB RF attenuation
50 dB RF attenuation
-
If DB1 in 5F 0 -
position in a line.
-
x
x
0
x
x
l
x
x
x
x
0
x
x
x
0
x
60 dB RF attenuation
829 MHz 2nd converter -
1 Character is a space
0 Character is not a
x
x
x
x
o
x
x
O
x
x
x
x
x
x
x
x
2 GHz 2nd converter
RF INPUT
-
space
-
If DB1 in 5F 0 -
x x x x O x x x 100 ms to switch attenuator
Power Supplies Status
-
1 Skip a line
-
0 Don't skip a line
If DB1 in 5F 0 -
(CF) Character code (lower 6
x x x x x x l x Fault bits of ASCII)
x x x x x x O x Supplies okay
G. Sweep
F. Crt Readout
Crt Control (5F)
1 x x x x x x x Extended Address 1
l x x x x x x x Spectrum chop enable x l x x x x x x Extended Address 0
O x x x x x x x Spectrum chop disable x x l x x x x x Marker DAC/Ramp Gen-
x l x x x x x x 32 characters/line erator
x O x x x x x x 40 characters/line x x x x l x x x Trigger Single Sweep
x x l x x x x x 2 lines x x x x x l x x Disable Sweep Gate
x x O x x x x x 16 lines x x x x x x l x Didsable Trigger
x x x x l x x x Max span dot on x x x x x x x l Abort Sweep
x x x x O x x x Max span dot off
x x x x x x l x Address 2F contains an Extended Address Subaddress bits for Port
address 1 and Address 2 OF giving subaddresses
x x x x x x o x Address 2F contains data 3-0. Subaddresses 0 and
x x x x x x x l Readout enabled 1 have the rest of the
x x x x x x x o Readout disabled to load control bits not on
readout Address IF. Subad-
A8 (address bit 8) dresses 2 and 3 receive
A9 (address bit 9) the 12 bits to set the
DAC.
Maintenance - 275412754P Service Vol. 1
Table 6-10 Icontl Table 6-10 (cont)
Data Bits Data Bits
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Description
G. Sweep H. Span Attenuator
Holdoff, Interrupt, Trigger Span Magnitude (75)
(0 F. 0) Lower 8 bits of 10-
x x O O x x x x Short sweep holdoff bit attenuation code
X X O l x x x x Medium sweep holdoff (000 is max attenua-
x x l o x x x x Long sweep holdoff tion)
x x x x 0 0 x x Free run trigger mode
Span Magnitude
x x x x 0 1 x x Internal trigger mode
and Attenuator (76)
x x x x l o x x External trigger mode
x x x x l l x x Line trigger mode l x x x x x x x Gain of U3032 is +1
x x x x x x l x Enable end-of-sweep interupt O x x x x x x x Gain of U3032 is -1
x x x x x x x l Single Sweep Mode x 0 0 x x x x x x1.0 sweep decade
attenuator
Sweep Rate and Mode (OF.l) x0.1 sweep decade
x 0 1 x x x x x
x x x l l 0 1 1 20 ps Time/Div attenuator
x x x l 0 1 1 1 50 ps Time/Div x l O x x x x x x0.01 sweep decade
x x x 1 0 0 1 1 100 ps Time/Div attenuator
x x x o 1 0 1 1 200 ps Time/Div x x x 0 0 x x x 1st LO main coil out-
x x x o o 1 1 1 500 ps Time/Div put select and cali-
x x x o 0 0 1 1 1 ms Time/Div bration
x x x 1 1 0 0 1 2 ms Time/Div 1st LO FM coil out-
x x x 1 0 1 0 1 5 ms Time/Div put select and cali-
x x x 1 0 0 0 1 10 ms Time/Div bration
x x x o 1 0 0 1 20 ms Time/Div x x x l o x x x 2nd LO output select
x x x 0 0 1 0 1 50 ms Time/Div and calibration
x x x 0 0 0 0 1 100 ms Time/Div DB2 For future use
x x x 1 1 0 0 0 200 ms Time/Div DB1, DBO Upper two bits of
x x x 1 0 1 0 0 500 ms Time/Div attenuation code
x x x 1 0 0 0 0 1 s Time/Div
x x x 0 1 0 0 0 2 s Time/Div
x x x 0 0 1 0 0 5 s Time/Div
x x x 0 0 0 0 0 10 s Time/Div
x x x l l l l l Manual
X X X O l l l l External
Marker DAC value bits
Marker DAC value bits
Poll Bit
Maintenance - 2754/2754P Service Vol. 1
Table 6-10 (cont) Table 6-10 (cont)
Data Bits Data Bits
7 6 5 4 3 2 1 0 Description 7 6 5 4 3 2 1 0 Description
I 1st LO Driver
. J. Preselector
Driver (77)
1st LO Driver Functions
(72) 0 1 x x x x x x -conversion, 829 MHz offset
1 o x x x x x x +conversion, 829 MHz offset
1 x x x x x x x Normal span mode
0 0 x x x x x x 829 MHz IF not used
o x x x x x x x Max span mode
x x l x x x x x Driver output filter on (for
x l x x x x x x Connect sweep voltage to
narrow spans)
driver
x x o x x x x x Driver output filter off
Disconnect sweep voltage
x x x l x x x x Preselector switch
to driver
x x x o x x x x LPF switch
x x l x x x x x Driver off (for degauss)
x x x x l x x x 1st LO FM coil not swept
x x O x x x x x Driver on
x x x x O x x x 1st LO FM coil swept
x x x l x x x x Filter on at driver output (for
x x x x x l x x Driver on
unphase-locked narrow
x x x x x O x x Driver off (for degauss)
spans)
x x x x x x x l 3rd harmonic 1st LO conver-
x x x O x x x x Filter off at driver output
sion
x x x x l x x x External mixer disconnected
External mixer connected 1st harmonic 1st LO conver-
x x x x o x x x
(connected in bands 1-5 if sion
external mixer selected; K. CENTERIMKR
always connected in higher FREQUENCY Con-
bands) trol
x x x x x l l 0 lnternal mixer bias for Band
Control (70)
1
x x x x x 1 1 0 lnternal mixer bias for Band l x x x x x x x 1st LO storage gate open
2 o x x x x x x x 1st LO storage gate closed
X X X X X l l O lnternal mixer bias for Band x o x x x x x x Steers DAC data to 1st LO
3 high byte
x x x x x l 0 1 lnternal mixer bias for Band x x O x x x x x Steers DAC data to 1st LO
4 mid byte
X X X X X O l l lnternal mixer bias for Band x x x o x x x x Steers DAC data to 1st LO
5 low byte
x x x x x l l l No internal mixer bias x x x x l x x x 2nd LO storage gate open
selected x x x x o x x x 2nd LO storage gate closed
x x x x x o x x Steers DAC data to 2nd LO
PEAKing Control (7E)
high byte
O x x x x x x x Steers DB4-DBO to upper x x x x x x o x Steers DAC data to 2nd LO
latch mid byte
x O x x x x x x Steers DB5-DBO to lower x x x x x x x o Steers DAC data to 2nd LO
latch low byte
DB5-DBO 1 sent to DB4 of upper latch
DAC Data (71)
disables front-panel PEAK-
ing control; DB3-DBO of Data for center frequency
upper latch and DB5-DBO DAC(s) steered by control
of lower latch form 10-bit register
input to DAC for program- CENTERIMKR FREQUENCY
mable peaking voltage Control Read (FO)
DB7 1st LO DAC stored voltage
comparator
DBO 2nd LO DAC stored voltage
comparator
Maintenance - 275412754P Service Vol. 1
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