Service Manuals, User Guides, Schematic Diagrams or docs for : Western Digital _dataBooks 1992_SystemLogic_Imaging_Storage 04_WD76C10A
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WD76C1 OAILPIL V
TABLE OF CONTENTS
Section Title Page
1.0 INTRODUCTION 4-1
1.1 Document Scope 4-1
1.2 Features 4-1
1.3 General Description 4-1
1.3.1 WD76C10A 4-1
1.3.2 WD76C10ALP 4-2
1.3.3 WD76C10ALV 4-2
2.0 ARCHITECTURE 4-4
2.1 Initialization And Clocking 4-4
2.2 AT Bus . . . . . . . 4-4
2.3 Main Processor Control 4-4
2.4 Numeric Processor Control 4-4
2.5 Data Bus . . . . . . . 4-4
2.6 Memory And EMS Control 4-4
2.7 Power Management Control 4-5
2.8 Register File . . . . . . 4-5
2.8.1 Lock Status Register 4-5
2.8.2 Lock/Unlock Register 4-6
3.0 SIGNAL DESCRIPTION . . . . 4-10
4.0 INITIALIZATION AND CLOCKING 4-21
4.1 Power Up Reset 4-21
4.2 Clocking 4-21
4.2.1 Internal Clock (CLK14) 4-21
4.2.2 System Bus Clock (SYSCLK) 4-21
4.2.3 Processor Clock (CPUCLK) . 4-21
4.2.4 CPU Clock (CPUCLK) Control Register 4-23
5.0 AT BUS 4-26
5.1 Interrupt Multiplexing ....... . 4-26
5.1.1 Data Acknowledge DACK7-5, 3-0 4-26
5.1.2 Data Request DROIN 4-26
5.1.3 Interrupt Requests . . . . . . 4-26
5.1.4 AT Address Bus, Data Bus, And Terminal Count (TC) Signal 4-26
5.2 Power Management Control PMCIN ............. 4-26
5.3 Numeric Processor . . . . . . . . . . . . . . . . . . . . 4-28
5.3.1 Numeric Processor Busy, Bus Timing, And Power Down Register 4-28
5.3.2 Numeric Processor Busy (NPBUSY) Reset 4-30
5.3.3 Numeric Processor Reset (NPRST) . . . . . . . . . . . . 4-30
aee ADVANCED INFORMATION 11/25/91 4-i
WD76C10AILPIL V
Section Title Page
5.4 DMA Control 4-31
5.4.1 Transfer Modes 4-31
5.4.2 Transfer Types 4-31
5.4.3 Autoinitialize 4-32
5.4.4 Priority 4-32
5.4.5 Extended Write 4-32
5.4.6 Base And Current Address 4-32
5.4.7 Base And Current Word Count 4-32
5.4.8 Command Register 4-34
5.4.9 Status Register 4-34
5.4.10 Request Register 4-34
5.4.11 Mask Registers 4-34
5.4.11.1 Single Mask Register 4-35
5.4.11.2 Clear Mask Register 4-35
5.4.11.3 Mask Multiple Register 4-35
5.4.12 Mode Register 4-35
5.4.13 Clear Pointer Register 4-36
5.4.14 Master Clear Register 4-36
5.4.15 DMA Mode Shadow Register 4-37
5.5 System Controller 8259 Interrupt Controllers 4-37
5.5.1 Interrupt Sequence 4-37
5.5.2 Setup - Initialization Command Words (ICW) 4-39
5.5.2.1 ICW1 -Initialization Command Word 1 4-39
5.5.2.2 ICW2 -Initialization Command Word 2 4-39
5.5.2.3 ICW3 - Initialization Command Word 3 4-39
5.5.2.4 ICW4 - Initialization Command Word 4 4-40
5.5.3 Operation 4-40
5.5.3.1 OCW1 - Operation Control Word 1 4-40
5.5.3.2 OCW2 - Operation Control Word 2 4-41
5.5.3.3 OCW3 - Operation Control Word 3 4-41
5.6 System Controller 8254 Timer 4-42
5.6.1 Setup 4-43
5.6.1.1 Mode 0 Interrupt On Terminal Count 4-43
5.6.1.2 Mode 1 Hardware Retriggerable One Shot 4-43
5.6.1.3 Mode 2 Rate Generator 4-43
5.6.1.4 Mode 3 Square Wave Generator 4-43
5.6.1.5 Mode 4 Software Triggered Strobe 4-43
5.6.1.6 Mode 5 Hardware Triggered Strobe 4-43
5.6.2 Reading The Counter 4-44
5.6.3 Reading Status 4-44
5.6.4 Page 4-44
5.6.5 Refresh Address 4-44
4-ii ADVANCED INFORMATION 11/25/91
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WD76C10AlLPIL V
Section Title Page
5.7 System Controller Decode 4-45
5.7.1 Page Register Decodes 4-45
5.8 NMI And Real-Time Clock 4-46
5.8.1 Real-Time Clock Address Register 4-46
5.8.2 Real-Time Clock Data Register . . 4-46
5.8.3 Lock Pass, Alternate A20G, And Hot Reset Register 4-46
5.9 Parity Error And 1/0 Channel Check 4-47
6.0 MEMORY AND EMS CONTROL 4-48
6.1 DRAM Address And Data Bus 4-48
6.2 Memory Configuration . . . 4-49
6.2.1 Memory Control . . 4-49
6.2.2 Memory Bank 3 Through Bank 0 Starting Address 4-51
6.2.3 Split Starting Address ..... . 4-52
6.2.4 RAM Shadow And Write Protect 4-54
6.2.5 High Memory Write Protect Boundary 4-56
6.3 Memory Timing ........... . 4-57
6.3.1 Non-page Mode DRAM Memory Timing 4-57
6.3.2 Page Mode ..... . 4-60
6.3.3 Memory Address Multiplexer . . . . . 4-61
6.4 EMS . . . . . . . . . . . . . . . . . . 4-63
6.4.1 EMS Control And Lower EMS Boundary 4-63
6.4.2 EMS Page Register Pointer 4-64
6.4.3 EMS Page Register . . . . . . . . 4-66
7.0 PORT CHIP SELECT AND WD76C10ALP REFRESH CONTROL 4-67
7.1 Refresh Control, Serial And Parallel Chip Selects 4-67
7.2 RTC, PVGA, 80287 liming, Disk Chip Selects 4-69
7.3 Programmable Chip Select Address ..... 4-71
7.4 Cache Flush . . . . . . . . . . . . . . . 4-71
7.5 1/0 Port Addresses And Chip Select Assignments 4-72
8.0 POWER MANAGEMENT CONTROL 4-74
8.1 System Activity Monitor (SAM) 4-74
8.2 Processor Power Down Mode 4-75
8.3 PMC Output Control Registers 4-78
8.4 PMC Timers . . . . 4-79
8.5 PMC Inputs 4-80
8.6 PMC Interrupt Enables 4-81
8.7 NMI Status 4-82
8.8 SeriallParaliel Shadow Register 4-82
8.9 Interrupt Controller Shadow Register 4-83
8.10 Port 70 Shadow Register . . . . . 4-84
ADVANCED INFORMATION 11/25/91 4-iii
WD76C10AILPIL V
Section Title Page
8.11 Activity Monitor Control Register 4-85
8.12 Activity Monitor Mask Register 4-87
8.13 Save And Resume 4-89
9.0 DIAGNOSTIC MODE 4-90
9.1 Diagnostic Register 4-90
9.2 Delay Line Diagnostic Register 4-92
9.3 Test Enable Register 4-93
9.4 Test Status Register . . . . 4-94
10.0 DC ELECTRICAL SPECIFICATIONS 4-95
10.1 Maximum Ratings . . . . . 4-95
10.2 DC Operating Characteristics 4-95
11.0 AC Operating Characteristics . . . 4-98
11 .1 Memory liming . . . . . . 4-100
11.1.1 80286 Page Mode liming 4-100
11.1 .2 80286 Non-Page Mode 00 Timing 4-106
11 .1 .3 80286 Non-Page Mode 01 Timing 4-110
11.1.4 80386SX Page Mode liming . . 4-113
11.1.5 80386SX Non-Page Mode 00 And Mode 01 Timing 4-118
11.2 AT Bus Timing . . . . . . . . . 4-123
11.2.1 CPU Initiated AT Bus Cycles 4-123
11.2.2 Entering The AT Bus 4-135
11.2.3 Exiting The AT Bus 4-140
11.2.4 DMA Cycles 4-145
11.2.5 AT Bus Master 4-150
11.2.6 AT Bus Refresh 4-156
11 .3 Processor Timing . 4-158
12.0 PACKAGE DIMENSIONS 4-171
APPENDIX
AO DC ELECTRICAL SPECIFICATIONS 4-172
A1 Maximum Rating 4-172
A2 DC Characteristics 4-172
A3 AC Operating Characteristics 4-175
A.4 80386SX Page Mode liming 4-176
4-iv ADVANCED INFORMATION 11125191
WD76C10AlLPIL V
LIST OF TABLES
Table Title Page
2-1 Register Index 4-8
3-1 Signal/Pin Assignments 4-10
3-2 Signal Description 4-11
4-1 Clock Switch Selection 4-24
4-2 Speedup Activity 4-24
5-1 MXCTL2-0 Decoding 4-27
5-2 Bus Timing Parameters 4-30
5-3 DMA Transfer Types 4-31
5-4 DMA Controller/channel Function Map 4-33
5-5 Interrupt Sequence 4-37
5-6 Interrupt Controller Function Map 4-38
5-7 Control Word Format 4-42
5-8 Decode Addresses 4-45
5-9 Page Register Decodes 4-45
6-1A Typical DRAM Speeds 4-57
6-1 B Non-Page Mode Timing 4-59
6-2 Page Mode Wait States 4-60
6-3 Page Mode Dram Address Multiplexer Configuration 4-61
6-4 Non-Page Non-Interleave Address Configuration 4-62
6-5 Non-Page 2-way Interleave Address Configuration 4-62
6-6 Upper Page Frame Assignments 4-64
6-7 Lower Page Frame Assignments 4-65
7-1 I/O Address And Chip Select Assignments 4-72
8-1 PMC Output Signals 4-78
8-2 PMCIN Inputs 4-81
9-1 Extended Version Number 4-90
9-2 Diagnostic Tests 4-91
10-1 DC Operating Characteristics 4-95
11-1 Timing Figure/Table Numbers 4-98
11-2 Signal Loading 4-99
11-3 80286 - Page Mode Memory Timing 4-100
11-4 80286 - Non-Page Mode 00 Memory Timing 4-106
11-5 80286 - Non-Page Mode 01 Memory Timing 4-110
11-6 80386sx - Page Mode Memory Timing 4-113
11-7 80386sx - Non-page Mode 00 And Mode 01 Memory Timing 4-118
11-8 CPU Initiated AT Bus Cycles 4-123
11-9 Entering The AT Bus 4-135
11-10 Exiting The AT Bus 4-140
11-11 DMA Cycles 4-145
11-12 AT Bus Master Cycle 4-150
ADVANCED INFORMATION 11/25/91 4-v
WD76C10AILPILV
Table Title Page
11-13 AT Bus Refresh Cycle, Default Timing 4-156
11-14 80286 CPU Timing . . . . 4-158
11-15 80386SX CPU Timing . . . 4-164
A.1 DC Operating Characteristics 4-172
A.2 Signal Loading ..... 4-175
A.3 80386SX - Page Mode Memory Timing 4-176
A.4 80386SX CPU Timing . . . . . . . 4-177
4-vi ADVANCED INFORMA TlON 11/25/91
WD76C10AILPILV
LIST OF ILLUSTRATIONS
Figure Title Page
1-1 System Block Diagram 4-3
2-1 WD76C10A/LP/LV Block Diagram 4-7
4-1 Clock Control 4-22
5-1 MXCTL2-0 Multiplexing 4-27
6-1 Split Size . 4-53
6-2 X_MEM = 0 . . . . . 4-55
6-3 X_MEM = 1 . . . . . 4-55
8-1 Register Access By Keyboard Controller 4-77
8-2 Power-Down .......... . 4-89
8-3 Power-Up ........... . 4-89
11-1 80286 - Page Mode First Access Readlwrite 4-101
11-2 80286 - Page Mode Read Cycle Followed By Page Hit 4-102
11-3 80286 - Page Mode Read After Write . . . . . 4-102
11-4 80286 - Page Mode, Page Miss Readlwrite 4-103
11-5 80286 - Page Mode, Write Miss Following Write 4-104
11-6 80286 - Page Mode Read Hit Followed By A Write Hit 4-105
11-7 80286 - Non-Page Mode 00,1 Wait State Write (4072H = 0001) 4-107
11-8 80286 - Non-Page Mode 00, 1 Wait State Read (4072H = 0001) 4-108
11-9 80286 - Non-Page Mode 00, 2 Wait States Read After Write (4072H = 0001) 4-109
11-10 80286 - Non-Page Mode 01, 0 Wait State Write (4072H = 3560H) 4-111
11-11 80286 - Non-Page Mode 01, 0 Wait State Read (4072H = 3560H) 4-112
11-12 80386SX - Page Mode, First Access Read/write ..... 4-114
11-13 80386SX - Page Mode, Page Miss Readlwrite . . . . . . 4-115
11-14 80386SX - Page Mode, Read Cycle Followed By A Page Hit 4-116
11-15 80386SX - Page Mode, Read After Write ....... . 4-116
11-16 80386SX - Page Mode, Read Hit Followed By A Write Hit 4-117
11-17 80386SX - Page Mode, Write Miss Cycle Following A Write Cycle 4-117
11-18 80386SX - Non-page Mode 00, 1 Wait State (Pipline) (4072H = 0001) 4-119
11-19 80386SX - Non-page Mode 00, 1 Wait State Write (Pipeline) (4072H = 0001) 4-120
11-20 80386SX - Non-Page Mode 01, 0 Wait State Read (Pipeline) (4072H = 3560H) 4-121
11-21 80386SX - Non-Page Mode 01, 0 Wait State Read (Pipeline) (4072H = 3560H) 4-122
11-22 AT Bus liD Or Memory Read: 8-Bit, Default Timing 4-125
11-23 AT Bus liD Or Memory Read: 8-Bit, Zerows Asserted 4-126
11-24 AT Bus liD Or Memory Read: 8-Bit Extra Wait State Added . 4-127
11-25 AT Bus liD Or Memory Write: 8-Bit, Even Byte, Default Timing 4-128
11-26 AT Bus liD Or Memory Write: 8-Bit, Odd Byte, Default Timing 4-129
11-27 AT Bus liD Or Memory Read: 8-Bit, Word To Byte Conversion, Default Timing 4-130
11-28 AT Bus liD Or Memory Write: 8-Bit, Word To Byte Conversion, Default Timing 4-131
11-29 AT Bus liD Or Memory Read: 16-Bit, Default Timing . . . . . . . . . . 4-132
11-30 AT Bus liD Or Memory Read: 16-Bit, OWS Asserted And Extra Wait State Added 4-133
ADVANCED INFORMATION 11125/91 4-vii
WD76C10AILPIL V
Figure Title Page
11-31 AT Bus I/O Or Memory Write: 16-Bit, Default Timing 4-134
11-32 80286 CPU - Asynchronous CPUCLK To SYSCLK, BREQ Delay = 1/2 Clock 4-136
11-33 80286 CPU - Asynchronous CPUCLK To SYSCLK, BREQ Delay = 1 Clock 4-136
11-34 80286 CPU - Synchronous CPUCLK To SYSCLK 4-137
11-35 80386SX CPU - Asynchronous CPUCLK To SYSCLK, BREQ Delay = 1/2 Clock 4-138
11-36 80386SX CPU - Asynchronous CPUCLK To SYSCLK, BREQ Delay = 1 Clock 4-138
11-37 80386SX CPU - Synchronous CPUCLK To SYSCLK 4-139
11-38 Synchronous AT Bus Cycle Completion, AT Bus Clock = CPUCLK + 2 4-141
11-39 Synchronous AT Bus Cycle Completion, AT Bus Clock = CPUCLK + 1 4-142
11-40 Asynchronous AT Bus Cycle Completion, BAK_DEL = -1 OR -0.5 AT Bus Cycles 4-143
11-41 Asynchronous AT Bus Cycle Completion, BAK_DEL = 0 OR +0.5 AT Bus Cycles 4-144
11-42 Basic DMA Cycle, Default Timing 4-147
11-43 DMA Cycle, 8-Bit I/O To On-Board Memory 4-148
11-44 DMA Cycle, On-Board Memory To 8-Bit I/O 4-149
11-45 AT Bus Master, Bus Acquisition/Release 4-153
11-46 AT Bus Master, Write To On-Board Memory 4-154
11-47 AT Bus Master, Read From On-Board Memory 4-155
11-48 AT Bus Refresh Cycle, Default Timing 4-157
11-49 80286 - CPU RES And NPRST During Power-Up 4-159
11-50 80286 - Coprocessor Reset (NPRST) Initiated By lOW To Port F1 4-159
11-51 80286 - Processor Reset (CPU RES) Initiated By Sources
Other Than Power-Up Reset 4-160
11-52 80286 - BUSYCPU Asserted During Coprocessor Access 4-161
11-53 80286 - Latching BUSYCPU When An Error Occurs And
Clearing It With A Write To Port FO 4-162
11-54 80286 - Miscellaneous Timing 4-163
11-55 80386SX - CPU RES NPRST During Power-Up 4-166
11-56 80386SX - Coprocessor Reset (NPRST) Initiated lOW To Port F1 4-166
11-57 80386SX - Processor Reset (CPU RES) Initiated By Sources
Other Than Power-Up Reset 4-167
11-58 80386SX - BUSYCPU Assertion During Coprocessor Access 4-168
11-59 80386SX - Latching BUSYCPU When An Error Occurs
And Clearing It With A Write To Port FO 4-169
11-60 80386SX - Miscellaneous Timing 4-170
11-61 80386SX - Input Setup And Hold Timing 4-170
11-62 80386SX - Output Delay Timing 4-170
12-1 132-Pin PQFP Package 4-171
4-viii ADVANCED INFORMATION 11125191
INTRODUCTION WD76C10AILPILV
1.0 INTRODUCTION
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