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MC68040_Designers_Handbook_1990


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MC68040
          DESIGNER'S HANDBOOK




   Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume
   any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights
   of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
   applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal
   injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and
   hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
   attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
   alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and @ are registered trademarks of Motorola, Inc. Motorola,
   Inc. is an Equal Opportunity/Affirmative Action Employer.




MOTOROLA INC.,             1990
PREFACE
 The complete documentation package for the MC68040 consist of the
 MC68040UM/AD MC68040 User's Manual, the M68000PM/AD M68000
 Programmer's Reference Manual, the MC68040/D MC68040 Technical Summary,
 and the MC68040DH/AD MC68040 Designer's Handbook.
 The MC68040 User's Manual describes the capabilities, operation, and
 programming of the MC68040 32-bit third-generation microprocessor. The M68000
 Programmer's Reference Manual contains the complete instruction set for all the
 M68000 family. The MC68040 Technical Summary. contains an overview of the
 MC68040 and includes the electrical specifications. The MC68040 Designer's
 Handbook contains applications and system design information.

 This Designer's Handbook is organized as follows:
   Section 1             Introduction
   Section 2             Instruction Timing
   Section 3             Floating-Point Emulation
   Section 4             MC68040 Thermal Considerations
   Section 5             Transmission Lines
   Section 6             SPICE
   Section 7             MC68040 To MC68030 Bus Adapter Application
   Section 8             IEEE P1149.1 Test Access Port
   Section 9             Bus Interface Considerations and Examples
   Appendix A            ASCII Conversion Table
   Appendix B            Product Support
                                            TABLE OF CONTENTS
Paragraph                                                                                                               Page
Number                                                     Title                                                       Number

                                                      Section 1
                                                    Introduction

1.1        Instruction Set Overview ..................................................................................1-1
1.2        Programming ModeL ...........................................................................................1-3
1.3        Addressing Modes..............................................................................................1-6

                                                          Section 2
                                                     Instruction Timing

2.1        Fetch Effective Address ....................................................................................2-1
2.2        Instruction Execution Times ..............................................................................2-3
2.3        MOVE Instruction Timing ...................................................................................2-7
2.4        Cache Maintenance ..........................................................................................2-10
2.4.1           Cache Invalidate Instruction Timing .......................................................2-10
2.4.2           Cache Push Instruction Timing ................................................................2-11



                                                        Section 3
                                                Floating-Point Emulation

3.1        Definitions, Acronyms,.and Abbreviations ....................................................3-1
3.2        Product Overview ...............................................................................................3-1
3.3        General Constraints ............................................................................................3-1
3.4        Assumptions and Dependencies .....................................................................3-2
3.5        Functional Requirements ...................................................................................3-2
3.5.1          Data Formats and Data Types ..................................................................3-2
3.5.2          Exceptions ....................................................................................................3-3
3.5.2.1              BSUN-Branch/Set on Unordered ..................................................3-3
3.5.2.2              SNAN-Signaling Not-a-Number ...................................................3-3
3.5.2.3              OPERR-Operand Error ...................................................................3-3
3.5.2.4              OVFL-Overflow................................................................................3-6
3.5.2.5              UNFL-Underflow...............................................................................3-6
3.5.2.6              DZ-Divide by Zero ...........................................................................3-7
3.5.2.7              INEX1/INEX2-lnexact Result 1/2 ..................................................3-7
3.5.3          Instructions....................................................................................................3-7
3.5.3.1              Arithmetic .............................................................................................3-7
3.5.3.2              Transcendental ...................................................................................3-8
3.6        External Interface Requirements ......................................................................3-8
3.7        Performance Requirements ...............................................................................3-8
3.7.1          Speed.............................................................................................................3-8
3.7.2          Accu racy ......................................................................................................3-8
3.7.2.1              Arithmetic Instructions .......................................................................3-9

MOTOROLA                             MC68040 DESIGNER'S HANDBOOK                                                                iii
                           TABLE OF CONTENTS (Continued)
Paragraph                                                                                                                   Page
Number                                                      Title                                                          Number

                                                 Section 3 - Continued
                                                Floating-Point Emulation

3.7.2.2            Transcendental Instructions .............................................................3-9
3.7.2.3            Decimal Conversions ........................................................................3-9
3.7.3        Compatibility .................................................................................................3-9
3.8       Other Requirements ............................................................................................3-9
3.8.1         Maintainability..............................................................................................3-9
3.8.2         Packagin'g .....................................................................................................3-9
3.8.3         Site Adaptions ..............................................................................................3-9
3.8.4         Stack Area Usage.......................................................................................3-1 0
3.8.5         ROM-based Applications .........................................................................3-10
3.9       FPSP Kernel Version Installation Notes ........................................................3-10
3.9.1         Differences between the MC68040 and MC68882 Floating-Point
              Exception Handling ....................................................................................3-1 0
3.9.2         Vector Table ................................................................................................3-12
3.9.3         FPSP Supplied Entry Points .....................................................................3-1 3
3.9.4         Extract the Hardware Independent Portion of the MC68882
                Handlers .....................................................................................................3-1 3
3.9.5         MC68040 Minimum Exception Code ......................................................3-1 4
3.9.6         Mem_read and Mem_write .......................................................................3-15
3.9.7         Increasing F-Line Handler Performance ............................................... 3-15
3.9.8         Stack Area Usage.......................................................................................3-1 5
3.9.9         ROM-based Applications .........................................................................3-16
3.10      References ..........................................................................................................3-16

                                                  Section 4
                                        MC68040 Thermal Considerations

4.1       MC68040 Thermal Device Characteristics ...................................................4-1
4.1.1         The MC68040 Die and Package ..............................................................4-1
4.1.2         MC68040 Power Considerations .............................................................4-2
4.1.2.1              The MC68040 Output Buffer Mode .................................................4-2
4.1.2.2              Relationships Between Thermal Resistances and
                      Temperatures ......................................................................................4-3
4.2       Thermal Management Techniques .................................................................4-4
4.2.1         MC68040 Thermal Characteristics in Still Air....................................... .4-4
4.2.2         MC68040 Thermal Characteristics in Forced Air ................................ .4-5
4.2.3         MC68040 Thermal Characteristics with a Heat Sink ........................... .4-5
4.2.4         MC68040 Thermal Characteristics with a Heat Sink and Forced
              Air ...................................................................................................................4-7
4.3       MC68040 Thermal Testing Summary ..............................................................4-8



iv                                   MC68040 DESIGNER'S HANDBOOK                                                     MOTOROLA
                         TABLE OF CONTENTS (Continued)
Paragraph                                                                                                              Page
Number                                                   Title                                                        Number

                                                      Section 5
                                                  Transmission Lines

5.1      Overview ..............................................................................................................5-2
5.2      PCD Traces ..........................................................................................................5-3
5.2.1         PCB Traces as Transmission Lines .........................................................5-3
5.2.2         PCB Trace Types ........................................................................................5-5
5.2.3         Device Loading ...........................................................................................5-9
5.3.     Transmission Line Analysis Techniques .......................................................5-11
5.3.1         Lattice Diagram ...........................................................................................5-12
5.3.2         Bergeron Plot. ..............................................................................................5-1 7
5.4      Terminations ........................................................................................................5-21
5.4.1         Series Termination Resistor ......................................................................5-22
5.4.2         Parallel Termination Resistor....................................................................5-22
5.4.3         Thevenin Network ......................................................................................5-22
5.4.4    RC Network..........................................................................................................5-23
5.4.5    Diode Network ....................................................................................................5-23
5.5      Miscellaneous Factors .....................................................................................5-23
5.5.1         Supply Voltage ...........................................................................................5-23
5.5.2         Temperature .................................................................................................5-23
5.5.3         Process .........................................................................................................5-23
5.5.4         Crosstalk.......................................................................................................5-24
5.5.5         Layout ...........................................................................................................5-24
5.6      Time-Domain Reflectometer .............................................................................5-24
5.7      Conclusion ..........................................................................................................5-25
5.8      Loaded Microstrip - Example 1.......................................................................5-25
5.8.1         Microstrip Geometry...................................................................................5-25
5.8.2         Consider Loading .......................................................................................5-25
5.8.3         Transmission Line Effects .........................................................................5-26
5.9      Loaded Stripline - Example 2 ..........................................................................5-26
5.9.1         Stripline Geometry ......................................................................................5-26
5.9.2         Consider Loading .......................................................................................5-27
5.9.3         Transmission Line Effects .........................................................................5-27
5.10     Lattice Diagram - Example 3 ...........................................................................5-27
5.10.1        Calculate Zo' and Tpd' ..............................................................................5-28
5.10.2        Switching Levels ........................................................................................5-28
5.10.3        Output High to Output Low .......................................................................5-28
5.10.4        Calculate Reflection Coefficients ............................................................5-28
5.10.5        Output Low to Output High .......................................................................5-29
5.10.6        Calculate Reflection Coefficients ............................................................5-30
5.11     Lattice Diagram with Series Termination - Example 4 ................................ 5-31
5.11.1        Series Termination ......................................................................................5-31
5.11.2        Output High-to-Low Switching Case ......................................................5-31
5.11.3        Recalculate ps ............................................................................................5-31

MOTOROLA                           MC68040 DESIGNER'S HANDBOOK                                                                 v
                          TABLE OF CONTENTS (Continued)
Paragraph                                                                                                                 Page
Number                                                     Title                                                         Number

                                                 Section 5 - Continued
                                                  Transmission Lines

5.11.4        Calculate Voltages .....................................................................................5-32
5.11.5        Output Low-to-High Switching ................................................................5-33
5.11.6        Calculate Reflection Coefficients ............................................................5-33
5.12     Lattice Diagram with Parallel Termination - Example 5 ..............................5-34
5.12.1        High-to-Low Switching ..............................................................................5-35
5.12.2        Recalculate Reflection Coefficients .......... :.............................................5-35
5.12.3        Calculate Voltages .....................................................................................5-35
5.12.4        Re-calculate Reflection Coefficients ......................................................5-36
5.12.5        Output Low-to-High Switching ................................................................5-37
5.12.6        Calculate Reflection Coefficients ............................................................5-37
5.13     Bergeron Plot - Example 6 ...............................................................................5-39
5.13.1        Calculate ZO' ............................................................................................... 5-39
5.13.2        Bergeron Plot Method ................................................................................5-39
5.13.3        Summary.......................................................................................................5-41
5.14     Bergeron Plot for Devices with High-Drive Capabilities - Example 7..... 5-43
5.14.1        Trace Characteristics ................................................................................5-43
5.14.2        Calculate Effects of Load ..........................................................................5-43
5.15     Bergeron Plot with Parallel Termination - Example 8 ................................ 5-46
5.16     Bergeron Plot for a Hefty Output Driving Device Connected to a Lightly Loaded
         Trace - Example 9 .............................................................................................. 5-4 7
5.17     Bergeron Plot for Series Termination - Example 10 ................................... 5-49
5.18     References ..........................................................................................................5-51

                                                    Section 6
                                             SPICE Module Information




                                          Section 7
                           MC68040 TO MC68030 Bus Adapter Application

7.1      Compatibility.........................................................................................................7-2
7.1.1        Software.........................................................................................................7-2
7.1.2        Hardware .......................................................................................................7-2
7.2      Configurations ......................................................................................................7-2
7.3      Overview ..............................................................................................................7-3
7.3.1        Units ................................................................................................................7-3
7.3.2        Operation ......................................................................................................7-4
7.4      Signal Identification ............................................................................................7-5

vi                                  MC68040 DESIGNER'S HANDBOOK                                                     MOTOROLA
                            TABLE OF CONTENTS (Continued)
Paragraph                                                                                                                Page
Number                                                      Title                                                       Number

                                       Section 7 - Continued
                             MC68040 TO MC68030 Bus Adapter Application

7.4.1           MC68040 Signal Connections .................................................................7-7
7.4.2           MC68030 Signal Connections .................................................................7-7
7.4.3           MC68040 to MC68030 Signal Connections ..........................................7-8
7.4.4           Miscellaneous Signals ...............................................................................7-9
7.4.5           Unsupported Signals ..................................................................................7-10
7.5          Bus Adapter Operation ....................................................................................7 -11
7.5.1           Main Control Unit ........................................................................................7-11
7.5.1.1              Control PAL ........................................................................................7-11
7.5.1.2              Output Enable PAL ..........................................................................7-14
7.5.1.3               Latch Enable PAL ............................................................................7-19
7.5.1.4              Termination Generation, AS,DS PAL. ...........................................7-20
7.5.2           Data Bus Buffers .........................................................................................7-21
7.5.3           Internal Termination Generation ..............................................................7-21
7.5.4           Transfer Attribute Translation ...................................................................7-24
7.5.5           Bus Arbitration .............................................................................................7-24
7-6         Schematics and Parts .......................................................................................7-27
7-7         PAL coding ..........................................................................................................7-37
7-7.1           MC68040 Bus-Translator Control PAL. .................................................7 -37
7-7.2           MC68040 Bus-Translator Termination Generation PAL. .................... 7-49
7-7.3           MC68040 Bus-Translator Output Enable PAL. .................................... 7-51
7-7.4           MC68040 Bus-Translator Master PAL. ..................................................7-54
7-7.5           MC68040 Bus-Translator Bus Arbitration PAL .................................... 7-58
7.7.6           MC68040 Bus Translator Output Enable PAL. .................................... .7-61
7-8         Timing Examples.................................................................................................7-66

                                                     Section 8
                                           IEEE P1149.1 Test Access Port

8.1         Overview ..............................................................................................................8-1
8.2         Instruction Register .............................................................................................8-2
8.2.1            EXTEST (000) ..............................................................................................8-3
8.2.2            BYPASS (11 X, 001) ...................................................................................8-9
8.2.3            SAMPLE/PRELOAD (01 X) .......................................................................8-9
8.2.4            SHUTDOWN (1 OX) ...................................................................................... 8-9
8.2.5            BYPASS (11 X) ............................................................................................8-10
8.3         MC68040 Restrictions .......................................................................................8-1 0
8.4         Non-IEEE P1149.1 Operation .........................................................................8-11
8.5       . JTAG Electrical Specifications .......................................................................8-12
8.5.1            DC Electrical Characteristics ...................................................................8-1 2
8.5.2       IEEE 1149.1 Preliminary Timing Specifications ........................................... 8-13


MOTOROLA                              MC68040 DESIGNER'S HANDBOOK                                                              vii
                        TABLE OF CONTENTS (Continued)
Paragraph                                                                                                           Page
Number                                                  Title                                                      Number


                                                 Section 9
                                         SRAM Interface Application

9.1     Byte Select Logic For The MC68040 .............................................................9-1
9.2     Memory Interface ................................................................................................9-2
9.2.1        Access Time Calculations ........................................................................9-4
9.2.2       Calculating Frequency-Adjusted MC68040 Output.. .......................... 9-6
9.2.3   Burst Mode Cycles .............................................................................................9-9
9.3     A 2-1-1-1 Burst Mode Memory Bank Using SRAMs ................................... 9-9
9-4     Schematics ..........................................................................................................9-25




                                                APPENDIX A
                                         ASCII CONVERSION TABLE

                                                  APPENDIX B
                                               PRODUCT SUPPORT




viii                              MC68040 DESIGNER'S HANDBOOK                                                  MOTOROLA
                                                             LIST OF FIGURES
Figure                                                                                                                                               Page
Number                                                                  Title                                                                       Number

1-1        Programming ModeL ...........................................................................................1 -4

2-1      MOVE Dy, Ox Pipeline Flow ............................................................................2-9
2-2      MOVE (ds,An, Dn),-(Ax) Pipeline Flow.........................................................2-9
2-3      MOVE (An),([Ax]) Pipeline Flow.....................................................................2-10
2-4      CINV Integer Instruction Flow..........................................................................2-11
2-5      CPUSH Example 1 .............................................................................................2-13
2-6      CPUSH Example 2 .............................................................................................2-13


4-1        Heat Sink Example ..............................................................................................4-6
4-2        Heat Sink with Attachment .................................................................................4- 7
4-3        MC68040 Relationship of 0JA and Air Flow ................................................4-8


5-1        Transmission Waveforms ...................................................................................5-1
5-2        Lumped Transmission Line Approximation ....................................................5-4
5-3        Cross-section Trace Diagrams .........................................................................5-6
5-4        Simplified Transmission Line Representation ...............................................5-10
5-5        Lattice Diagram ...................................................................................................5-1 4
5-6        Bergeron Plot ......................................................................................................5-1 8
5-7        Low-to-High Switching .....................................................................................5-20
5-8        Trace Terminations ............................................................................................5-21

7-1        MC68040 to MC68020/MC68030 Bus Adapter ...........................................7-1
7-2        Configuration for Daughter Board ....................................................................7-3
7-3        Bus Adapter Signal Connections .....................................................................7-6
                                                                                                                                                                 9
           ~i~TT~~~~g~~~ ~ ~ ~~ ~ ~~ ~~~ ~ ~ ~~ ~ ~~ ~ ~~ ~ ~ ~~ ~ ~~ ~ ~~~ ~ ~~ ::: ~~:~ ~~~ ~:~ ~ ~~:: ~~ ~~: ~ ~ ~::~:: ~:~::: ~:::~:: ~:::: ~::::: ~::::::::: ;_-1 0
7-4
7-5
7-6      Master State Diagram ........................................................................................7-12
7-7      Slave State Diagram ..........................................................................................7-14
7-8      Data Bus Connections ......................................................................................7-16
7-9      OEBUS Timing .....................................................................................................7 -1 8
7-10     Internal Termination Signal Timing ..................................................................7-22
7 -11    STERM Timing Requirements ...........................................................................7-23
7-12     Bus Arbitration State Diagram ..........................................................................7-26
7-13     Bus Adapter.........................................................................................................7 -29
7-14     MC68040 Processor Connections .................................................................7 -31
7-15     Control Unit ..........................................................................................................7-32
7-16     Data Bus Buffer Unit. ..........................................................................................7 -33
7-17     Internal Termination Generation ......................................................................7 -34
7-18     Transfer Attribute Translation ...........................................................................7 -35
7-19     Bus Arbitration ....................................................................................................7-36
7-20     Retry Timing Example ........................................................................................7-67
7-21     HALT Timing Example .......................................................................................7-69

MOTOROLA                                    MC6S040 DESIGNER'S HANDBOOK                                                                                        ix
                                LIST OF FIGURES (Continued)
Figure                                                                                                                 Page
Number                                                   Title                                                        Number

7-22     Bus Error Timing Example .................................................................................7-71
7-23     Long-Word Write to Word Port Example ........................................................7-73
7 -24    Word Write to Byte Port Example .....................................................................7 -7 5
7-25     Long-Word Read to Word Port Example ........................................................7-77
7-26     Long-Word Read to Byte Port Example ........................................................ .7-79

8-1      IEEE P1149.1 Test Logic Block Diagram .......................................................8-2
8-2      Output Latch Cell (0. Latch) ..............................................................................8-7
8-3      Input Pin Cell (I.Pin) ............................................................................................8-7
8-4      Output Control Cell (IO.Ctl) ...............................................................................8-8
8-5      Bypass Register..................................................................................................8-1 0
8-6      Clock Timing Diagram .......................................................................................8-13
8-7      TRST Timing Diagram ........................................................................................8-14
8-8      Boundary Scan Timing Diagram .....................................................................8-14
8-9      Test Access Port Timing Diagram ...................................................................8-15

9-1      MC68040 Write Byte Select Logic ...................................................................9-3
9-2      Access Time Computation Diagram ................................................................9-5
9-3      Signal Relationships to Clocks .........................................................................9-7
9-4      SRAM Configuration ..........................................................................................9-1 0
9-5      ramlwe PAL Equations ......................................................................................9-12
9-6      ramcs PAL Equations ........................................................................................9-15
9-7      bufferoe PAL Equations ....................................................................................9-16
9-8      rambe1 PAL Equations .....................................................................................9-19
9-9      rambe2 PAL Equations .................................... ;................................................9-22
9-10     MC68040 ............................................................................................................9-26
9-11     Control Unit ..........................................................................................................9-27
9-12     SRAM Data Buffers ............................................................................................9-28
9-13     SRAM Address Buffers .....................................................................................9-29
9-14     SRAM Bank Even ..............................................................................................9-30
9-15     SRAM Bank Odd ................................................................................................9-31




x                                  MC68040 DESIGNER'S HANDBOOK                                                   MOTOROLA
                                                   LIST OF TABLES
Table                                                                                                                  Page
Number                                                    Title                                                       Number

1-1      MC68040 Instruction Set ...................................................................................1-2
1-2      MC68040 Coprocessor Instructions ...............................................................1-2
1-3      Addressing Modes ..............................................................................................1-6

2-1        Single Effective Address Instruction FormaL ................................................2-1
2-2        Brief Format Extension Word .............................................................................2-2
2-3        Full Format Extension Word ..............................................................................2-2
2-4        Instruction Execution Times ..............................................................................2-3
2-5        MOVE with Single or Breif Format Source and Destinations EAs ............ 2-7
2-6        MOVE with Full Format Source and Destinations EAs ...............................2-8
2-7        CINV Timing ........................................................................................................2-10
2-8        CPUSH Best/Worst Case Timing .....................................................................2-11

3-1      Functions Provided by MC68040 ...................................................................3-3
3-2      Support for Data Types and Data Formats .....................................................3-4
3-3      Operand Errors Handled by the MC68040 ....................................................3-5
3-4      Operand Errors Handled by the FPSWP ........................................................3-5
3-5      DZ Exceptions Generated by the MC68040 .................................................3-7
3-6      DZ Exceptions Generated by the FPSWP .....................................................3-7
3-7      Arithmetic Instructions ........................................................................................3-9
3-8      Transcendental Instructions..............................................................................3-9

4-1      Maximum Power Dissipation for Output Buffer Mode Configurations ...... .4-3
4-2      Thermal Parameters with No Heat Sink or Air Flow ..................................... .4-4
4-3      Thermal Parameters with Forced Air Flow and No Heat Sink ................... .4-5
4-4      Thermal Parameters with Heat Sink and No Air Flow ................................. .4-7
4-5      Thermal Parameters with Heat Sink and Air Flow........................................ .4-8

5-1      Termination Types and Their Properties ........................................................5-22

7-1        MC68040 Signal Connections .........................................................................7-7
7-2        MC68030 Signal Connections .........................................................................7-8
7-3        MC68040 to MC68030 Signal Connections .................................................7-8
7-4        Miscellaneous Signals .......................................................................................7-9
7 -5       Buffer Assignments ............................................................................................7 -17
7-6        Read Cycle Sequence ......................................................................................7-19
7-7        Latch Enable Generation Summary ................................................................7-20
7-8        PAL Speed Grades (tpd) ...................................................................................7-27
7-9        Suggested PALs .................................................................................................7-27
7-10       Speed Path Equations.......................................................................................7-27

8-1      Instructions ...........................................................................................................8-3
8-2      Boundary Scan Bit Definitions ..........................................................................8-5
8-3      DC Electrical Characteristics ..........................................................................8-12
8-4      Timing Specifications ........................................................................................8-13

MOTOROLA                            MC68040 DESIGNER'S HANDBOOK                                                                xi
                           LIST OF TABLES (Continued)
Table                                                                                      Page
Number                                       Title                                        Number

9-1      Data Bus Activity for Byte, Word, and Long-Word Transfers ..................... 9-2
9-2      Memory Access Time Equations at 25 MHz..................................................9-6
9-3      CalculatedOutput Specifications for Selected Frequencies ..................... 9-8
9-4      Calculated tAVDV Values for Selected Frequencies .................................9-8




xii                         MC68040 DESIGNER'S HANDBOOK                               MOTOROLA
SECTION 1
   INTRODUCTION
   This manual provides application examples and other support information for the
   system designer using the MC68040 32-bit microprocessor and is designed as a
   dynamic document. This means that new applications and information are provided
   on a continuing basis.

1.1 INSTRUCTION SET OVERVIEW
   The instructions provided by the MC68040 are listed in Table 1-1 and 1-2. The
   instruction set has been tailored to support high-level languages and is optimized
   for those instructions most commonly executed; however, all instructions listed are
   fully supported. Many instructions operate on bytes, words, and long words, and
   most instructions can use any of the addressing modes of Table 1-3.
   The floating-point instructions for the MC68040 are a commonly used subset of the
   MC68881/MC68882 instruction set with new arithmetic instructions to explicitly
   select single- or double-precision rounding. The remaining unimplemented
   instructions are less frequently used and are efficiently emulated in software,
   maintaining compatibility with the MC68881/MC68882 floating-point
   coprocessors.
   The MC68040 instruction set includes MOVE16, a new user instruction allowing
   high-speed transfers of 16-byte blocks between external devices such as memory
   to memory or coprocessor to memory. For detailed information on the MC68040
   instruction set, refer to M68000PM/AD, M68000 Programmer's Reference Manual.




MOTOROLA                    MC68040 DESIGNER'S HANDBOOK                                  1-1
                           Table 1-1. MC68040 Instruction Set
       Mnemonic                 Description                  Mnemonic                Description
      ABCD         Add Decimal with Extend                  MOVE         Move
      ADD          Add                                      MOVEA        Move Address
      ADDA         Add Address                              MOVECCR      Move Condition Code Register
      ADDI         Add Immediate                            MOVESR       Move Status Register
      ADDQ         Add Quick                                MOVEUSP      Move User Stack Pointer
      ADDX         Add with Extend                          MOVEC        Move Control Register
      AND          Logical AND                              MOVEM        Move Multiple Registers
      ANDI         Logical AND Immediate                    MOVEP        Move Peripheral
      ASL,ASR      Arithmetic Shift Left and Right          MOVEQ        Move Quick
      Bcc          Branch Conditionally                     MOVES        Move Alternate Address Space
      BCHG         Test Bit and Change                      MULS         Signed Multiply
      BCLR         Test Bit and Clear                       MULU         Unsigned Multiply -
      BFCHG        Test Bit Field and Change                NBCD         Negate Decimal with Extend
      BFCLR        Test Bit Field and Clear                 NEG          Negate
      BFEXTS       Signed Bit Field Extract                 NEGX         Negate with Extend
      BEFXTU       Unsigned Bit Field Extract               NOP          No Operation
      BFFFO        Bit Field Find First One                 NOT          Logical Complement
      BFINS        Bit Field Insert                         OR           Logical Inclusive OR
      BFSET        Test Bit Field and Set                   ORI          Logical Inclusive OR Immediate
      BFTST        Test Bit Field                           PACK         Pack BCD
      BKPT         Breakpoint                               PEA          Push Effective Address
      BRA          Branch                                   PFLUSH       No Effect
      BSET         Test Bit and Set                         PLOAD        No Effect
      BSR          Branch to Subroutine                     PMOVE        Move to/from ACx Registers
      BTST         Test Bit                                 PTEST        Test Address in ACX Registers
      CAS          Compare and Swap Operands                RESET        Reset External Devices
      CAS2         Compare and Swap Dual Operands           ROL,ROR      Rotate Left and Right
      CHK          Check Register Against Bound             ROXL, ROXR   Rotate with Extend Left and Right
      CHK2         Check Register Against Upper and Lower   Rm           Return and Deallocate
                   Bounds
      CLR          Clear                                    RTE          Return from Exception
      CMP          Compare                                  RTR          Return and Restore Codes
      CMPA         Compare Address                          RTS          Return from Subroutine
      CMPI         Compare Immediate                        SBCD         Subtract Decimal with Extend
      CMPM         Compare Memory to Memory                 Scc          Set Conditionally
      CMP2         Compare Register Against Upper and       STOP         Stop
                   Lower Bounds                             SUB          Subtract
      DBcc         Test Condition, Decrement and Branch     SUBA         Subtract Address
      DIVS,DIVSL   Signed Divide                            SUBI         Subtract Immediate
      DIVU,DIVUL   UnsiQned Divide                          SUBQ         Subtract Quick
      EOR          Logical Exclusive OR                     SUBX         Subtract with Extend
      EORI         Logical Exclusive OR Immediate           SWAP         Swap Register Words
      EXG          Exchange Registers                       TAS          Test Operand and Set
      EXT,EXTB     Sign Extend                              TRAP         Trap
      ILLEGAL      Take IlIel1al Instruction Tr~            TRAPcc       Trap Conditionally
      JMP          Jump                                     TRAPV        Trap on Overflow
      JSR          Jump to Subroutine                       TST          Test Operand
      LEA          Load Effective Address                   UNLK         Unlink
      LINK         Link and Allocate                        UNPK         Unpack BCD
      LSL, LSR     Logical Shift Left and Right


                     Table 1-2. MC68040 Coprocessor Instructions
      cpBCC        Branch Conditionally                     cpRESTORE    Restore Internal State of
                                                                         Coprocessor
      cpDBcc       Test Coprocessor Condition,              cpSAVE       Save Internal State of Coprocessor
                   Decrement and Branch                     cpscc        Set Conditionally
      cpGEN        Coprocessor General Instruction          cpTRAPcc     Trap Conditionally




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