Service Manuals, User Guides, Schematic Diagrams or docs for : acer ACER NOTES Acer Extensa 4220 4620 - WISTRON BIWA Acer Extensa 4220 4620 - WISTRON BIWA - POWER SEQUENCE
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A B C D E
Biwa POWER TOPLOGY AND POWER SEQUENCING
CLK GEN
CK_PWRGD/PD#
DDR_VREF_S3
1D8V_S3 Host System Power DRAM
4 4
M State System Power Wells ME Clocking
PM_SLP_S4# TPS51100
3b DDR_VREF_S0 State Source
CLK_PWRGD
S5
PM_SLP_S3# S3
VTTREF
VTT
4b M0 S0 AC or
Battery
All wells
powered
Powered Clock chip powered and PLL
/DLL in use.
In self reflash;ME Clock chip powered with only
DCBATOUT 5V_AUX_S5 3D3V_AUX_S5 RTC_AUX_S5
9 M1 S3-S5 AC only
Main well down,
M rails down.
DRAM controller is
on,using Channel A
the GMCH clock running and
PLL/DLL in use.
1D8V_S3 1D8V_LDO_1D5V
A K G28 S3-S5 AC or Main well down, Powered off(or None, ME powered off.
ISL6236 G913 DCBATOUT
3a 2 1
M-off
Battery M rails down. self reflash
37
-3 34
ICH8M
1D05V_S0 1D8V_LDO_1D25V
1
GAP-OPEN-PWR
RTC_RST# RTCRST#
G64
R7
10KR2J-3-GP WPC8768L PM_PWRBTN# 2 PWRBTN# SLP_S4# 3 PM_SLP_S4#
MAX8717 2 1
ECRST# VCC_POR# GPIO23
5 PM_SLP_M# TP49 TPAD30 ON1 LX1
4a GAP-OPEN-PWR
2
R18 PGOOD1
2 SW1 1
1 2
470R2J-2-GP
KBC_PWRBTN# GPIO03 GPIO40 RSMRST#_KBC
-1
RSMRST# SLP_S3#
4 PM_SLP_S3# ON2 LX2
PGOOD2
CPUCORE_ON
3D3V_S0 S5_ENABLE PM_SLP_S4# PM_SLP_S3#
1 GPIO36 PLTRST# PLT_RST1# VCC_CORE_S0
1
5 C14 5V_Aux_S5 3D3V_S5 1D8V_S3 1D05V_S0
PCIRST# PCIRST1# DCBATOUT 5V_S0
4 3 SCD1U16V2ZY-2GP
14 7 3D3V_Aux_S5 5V_S5 DDR_VREF_S3 3D3V_S0
2
SW-TACT-59-GP-U1 CLPWROK CPUPG H_PWRGD
PWROK VRMPWRGD 5V_S0
62.40009.631
13 MAX8770 DDR_VREF_S0
6 SHDN# PWRGD VGATE_PWRGD
1D5V_S0
8
10 8
1D25V_S0
RTC_BAT A K
RTC
10 DCBATOUT
5V_S5 5V_S0
3
KBC_PWRBTN#_R
1 PWRSW1 3
-2 3D3V_S5 3D3V_S0
3
5 S5_ENABLE 1 2 ISL6236
EN1 PHASE1
0 1
U46
2
R385
2 0R2J-2-GP
2 4 3V/5V_EN POK1 U50
SW-TACT-103-GP-U PURE_HW_SHUTDOWN# 3 BAS16-1-GP 1 2
EN2 PHASE2 3V/5V_POK R372 2
62.40009.631 D31 POK2
1
0R2J-2-GP
1
1D5V_S0
1D8V_LDO_1D5V PM_SLP_S3#
DY Crestline
4b VGATE_PWRGD 1 R252 2 PWROK_GD 12 15 CPU
0R2J-2-GP 2 R255 1 PWROK
APL5912 PWROK PWROK 0R2J-2-GP
H_CPURST#
VOUT RESET# CPU_CPURST# RESET#
PM_SLP_S3# EN
POK
5912_POK 2 R328 1
0R2J-2-GP
CPUCORE_ON
PWROK
CPUCORE_ON
G792
10 1
R246
2
CLPWROK_MCH
0R2J-2-GP
11
CL_PWROK
RSTIN#
PWRGOOD
1D25V_S0
1D8V_LDO_1D25V
14
APL5915
4b PLT_RST1#
PLT_RST1#
H_PWRGD
PM_SLP_S3# EN
VOUT
5915_POK R229
13
2 1
POK 0R2J-2-GP PCIRST1#
TI 7412
level shift HDDDRV#_5 HDD
RESET#
2 2
Sequence of Events:
LPC debug BD
(-4)VccRTC active to RTCRST# inactive >18ms.
(-3)Insert ADT, ISL6236 output "5V_AUX_S5", G913(LP2951) output "3D3V_AUX_S5" when 5V_AUX_S5 ready.
(-2)WPC8768L asserts "S5_ENABLE", OR gate enables PWM IC for "5V_S5" ad "3D3V_S5". Mini Card
PESET#
(-1)WPC8768L drived "RSMRST#_KBC" to ICH8M(rise time 10%-90% <15ns)
(1)User push power botton : "KBC_PWRBTN#" to WPC8768L.
(2)"PM_PWRBTN#" from KBC to ICH8M. P2231 NEW Card
SYSRST#
(3)ICH8M asserts "PM_SLP_S4#" to enable PWM IC MAX8717 out "1D8V_S3".
1D8V_S3 regulator comes followed by "DDR_VREF_S3" regulators KBC WPC8768L
LRESET#
(3.1)SLP_S4# inactive to SLP_S3# inactive 1~4 RTCCLK.
(4)ICH8M asserts "PM_SLP_S3#" to enable PWM IC out "1D05V_S0".
After aprox 10ms soft start delay S0 power switches are turned on connecting S0 planes with S5/S3 planes. LAN BCM5787M
PERST#
5V_S5->"5V_S0",3D3V_S5->"3D3V_S0","1D8V_LDO_1D5V"->"1D5V_S0","1D8V_LDO_1D25V"->"1D25V_S0", "DDR_VREF_S3".
(4.1)V5REF(5V_S0) must be powered up before 3D3V_S0, or after winthin 0.7V. Also V5REF must power down after 3D3V_S0, or before within 0.7V.
(4.2)1D5V_S0 must power up before V_CPU_IO(1D05V_S0) or after winthin 0.7V. Also V_CPU_IO must power down before 1D5V_S0 or after within 0.7V.
(5)PM_SLP_M# : TP.
(6)When 3V, 5V, 1.8V, 1.05V ready, they are asserts "CPUCORE_ON" to PWM IC for CPU power.
(7)5ms after VCC_CORE_S0 regulation, VGATE_PWRGD is driven to ICH8M VRMPWRGD.
(8)"G792_PWROK" Output remains low while VCC is below the reset threshold,
1
and for 220ms after VCC rises above the reset threshold. 1
(9)10ms after "VGATE_PWRGD" plane comes up "CLK_PWRGD" is driven.
(10)Power OK for ICH8M(PWROK assertion indicates that PCICLK has been stable for at least 1ms, Vcc supplies active to PWROK >99ms) .
bom1
(10.1)VGATE_PWRGD active to PWROK active >3 ms.
(11)CL_PWROK Wistron Corporation
(12)POWER OK for GMCH 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
(13)"H_PWRGD" from ICH8M to CPU Title
(14)"PLT_RST1#"(PCIRST1#) from ICH8M to GMCH. POWER SEQUENCING
(14.1)PWROK active to PLTRST1# active 34~41 RTCCLK Size Document Number Rev
Biwa SA
(15)"H_CPURST#" from GMCH to CPU Date: Monday, October 16, 2006 Sheet 1 of 1
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