Service Manuals, User Guides, Schematic Diagrams or docs for : acer ACER NOTES Acer TravelMate 6252 6292 - QUANTA ZU1 - REV 3B
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5 4 3 2 1
ZU1 SYSTEM BLOCK DIAGRAM
PCI DEVICE IDSEL# REQ# / GNT# Interrupts CLOCK
DVI / 7307 CLOCK GENERATOR
Chrontel Merom 479 CPU
CB1410 AD17 REQ0# / GNT0# INTA# CK505/PCI1
CK505
(only for ezDock) uFCPGA Thermal Sensor
MR510 AD18 REQ1# / GNT1# INTB# CK505/PCI0
D D
Page 21 TIAB23 AD25 REQ2# / GNT2# INTE# CK505/PCI2
Page 2 Page 3
Page 3,4
S-VIDEO CONN FSB
Page 20
667/800 Mhz
DDRII
SDVO Dual Channel DDR2 SO-DIMM 0
LCD CONN TV 533/667 MHz
SO-DIMM 1 RJ45
(12.1"WXGA) LVDS NB Page 18
Page 20 VGA Page 12,13
Crestline
(GM965) Transformer
CRT Port Page 5~11 Page 18
Page 19
X4 DMI interface
Mini Card / Giga Lan
HDD (SATA) SATA
C
WLAN (BCM 5787)
C
Page 26
SB Page 27 Page 18
PATA PCIE-0 PCIE-1
ODD (PATA) PCI-Express
Page 26
USB 2.0 ICH8M
Azalia
Page 14~17
PCI Bus
USB Port x 3
USB0~2 Page 27
LPC
Bluetooth PCMCIA Card Reader
USB4 Page 27 1394
Controller Controller Controller
Finger Printer uR PC8763L Super I/O (CB 1410) (MR510)
USB6 Page 29 NS PC87383 (TI 43AB23)
Page 28 Page 30 Page 22 Page 23 Page 25
B B
CCD
USB8 Page 20
SPI ROM Touch Pad K/B CONN FIR PCMCIA Card Reader 1394 CONN
Page 28 Page 29 Page 29 Page 30 Page 24 Page 24 Page 25
A1A
(11/2):(1) Re-name.
HP HP AMP (2) Gerber out
Page 32 Page 31
5V/3V (ISL6236) 1.25V 1.5V 2.5V B1C
Audio Codec PCI-Express PCIE-2 (11/29):Gerber out
(ALC268) ezDockII/II+ Page 34 Page 38 C2A
INT SPK SPK AMP DVI (12/28):Gerber out
Page 32 Page 32 Connector USB3
USB VCORE(ISL6262A) Discharge D3A
PCIE , Lan ,1394 (2/12):Gerber out
Ser & Par Port 1394*2 Page 35 Page 38
Line in & MIC E3A
Page 32 Page 31 PS2 , VGA, DVI TV out / CRT (4/2):Gerber out
Switch
SPDIF,SM BUS Page 20
VTT 1.05V (SC411) Charger (ISL6251)
A
MediaBay A
Express Card Audio Page 36 Page 39
MDC 1.5 10/100/1G Switch 1.8V (TPS51116)
Page 31 Page 33 Page 18 PROJECT : ZU1
Page 37 Quanta Computer Inc.
Size Document Number Rev
Block Diagram 3B
Date: Tuesday, April 10, 2007 Sheet 1 of 39
5 4 3 2 1
5 4 3 2 1
Clock Generator E3A:(3/16) Change C542 from 0805(CH6102K9A01) to 0603(CH6101M9905) base on ME request(HDD Mylar issue)
Clock Gen I2C
L55
+3V C288 .1U_4
BKP1608HS181-T_6
C655
C542 0_6 C294 .1U_4 +3V
*4.7U_6 R436
10U_6 C287 10U_8
ICS9LPRS365BGLFT Q21
RHU002N06 R197
SLG8SP512T: AL8SP512K05
2
A1A:(9/24)
ICS FAE suggest to change C540 .1U_4 U19 10K_4
C542,C287 from 4.7uF to 10uF VDD_CK_VDD_PCI 2 48 A1A:(9/20) remove IO_VOUT 3 1 CGDAT_SMB
VDD_PCI IO_VOUT 13,16,18,27,33 PDAT_SMB
C292 .1U_4 VDD_CK_VDD_48 9
A1A:(9/28) VDD_CK_VDD_SRC VDD_48 CGCLK_SMB
16 VDD_PLL3 SCLK 64
D Reverse RC0603 footprint for EMI VDD_CK_VDD_REF 61 63 CGDAT_SMB D
VDD_REF SDA
0_6 C319 .1U_4 VDD_CK_VDD_SRC
CK505 +3V
39 VDD_SRC SRC5/PCI_STOP# 38 PM_STPPCI# 16
R199 VDD_CK_VDD_CPU 55 37 PM_STPCPU# 16 Q20
VDD_CPU SRC5#/CPU_STOP# RHU002N06 R195
2
+1.25V_VDD 12 54 CLK_CPU_BCLK_R RP36 1 2 0X2
VDD_96_IO CPU0 CLK_CPU_BCLK 3
0_6 C318 .1U_4 20 53 CLK_CPU_BCLK#_R 3 4 10K_4
VDD_PLL3_IO CPU0# CLK_CPU_BCLK# 3
R444 26 3 1 CGCLK_SMB
VDD_SRC_IO_1 13,16,18,27,33 PCLK_SMB
45 51 CLK_MCH_BCLK_R RP35 1 2 0X2
VDD_SRC_IO_3 CPU1 CLK_MCH_BCLK 5
36 50 CLK_MCH_BCLK#_R 3 4
VDD_SRC_IO_2 CPU1# CLK_MCH_BCLK# 5
49 VDD_CPU_IO
SRC8/ITP 47
A1A:(9/20) remove SATACLKREQ function, change R188 value from 475ohm to 22 ohm 46
SRC8#/ITP#
R188 22_4 PCI_CLK_510_R 1 35 CLK_PCIE_3GPLL#_R RP34 3 4 0X2
23 PCI_CLK_510 PCI0/CR#_A SRC10# CLK_PCIE_3GPLL# 6
SRC10 34 CLK_PCIE_3GPLL_R 1 2 CLK_PCIE_3GPLL 6 Pin Active Control signal
R434 33_4 PCI_CLK_CB714_R 3
22 PCI_CLK_CB714 PCI1/CR#_B
+3V R429 10K_4 33 PCIE_CLK_RBS_R R194 475_4 CLK_MCH_OE# 6
R433 33_4 PCLK_1394_R SRC11/CR#_H PCIE_CLK_RBS#_R R185 475_4 32 Low SRC9/9#
25 PCLK_1394 4 PCI2/TME SRC11#/CR#_G 32 PCIE_CLKREQ# 33
R187 33_4 PCLK_591_R 5 30 CLK_PCIE_EZ1_R RP29 3 4 0X2
28 PCLK_591 PCI3 SRC9 PCIE_CLK1+ 33
+3V R428 *10K_4 31 CLK_PCIE_EZ1#_R 1 2 PCIE_CLK1- 33
33 Low SRC10/10#
R431 22_4 PCI_CLK_SIO_R SRC9#
27,30 PCI_CLK_SIO 6 PCI4/SRC5_EN
R427 10K_4 44
R186 22_4 PCLK_ICH_R SRC7/CR#_F A1A:(9/24) Base on above table, SWAP SRC3 and SRC9
7 PCIF5/ITP_EN SRC7#/CR#_E 43
+3V R181 *10K_4
CG_XIN 60 41 CLK_PCIE_ICH_R RP37 1 2 0X2
15 PCLK_ICH XTAL_IN SRC6 CLK_PCIE_ICH 15
R182 10K_4 40 CLK_PCIE_ICH#_R 3 4
SRC6# CLK_PCIE_ICH# 15
CG_XOUT 59 XTAL_OUT CLK_PCIE_MINI1_R RP30 +3V
SRC4 27 3 4 0X2 CLK_PCIE_MINI1 27
R430 33_4 FSA 10 28 CLK_PCIE_MINI1#_R 1 2
16 CLKUSB_48 USB_48/FSA SRC4# CLK_PCIE_MINI1# 27
CLK_BSEL0 R426 2.2K_4
C CLK_BSEL1 CLK_PCIE_LAN_R RP31 C
57 FSB/TEST/MODE SRC3/CR#_C 24 3 4 0X2 CLK_PCIE_LAN 18
25 CLK_PCIE_LAN#_R 1 2 R184 10K_4 PCIE_CLKREQ#
SRC3#/CR#_D CLK_PCIE_LAN# 18
CLK_BSEL2 R441 10K_4 FSC 62 REF0/FSC/TESTSEL CLK_PCIE_SATA_R RP32
SRC2/SATA 21 3 4 0X2 CLK_PCIE_SATA 14
R442 22_4 8 22 CLK_PCIE_SATA#_R 1 2
16 14M_ICH VSS_PCI SRC2#/SATA# CLK_PCIE_SATA# 14
11 VSS_48
A1A:(9/24) Add PCIE_CLKREQ# PU to +3V
R443 22_4 15 17 DREFSSCLK_R RP41 1 2 0X2
30 SIO_14M VSS_IO SRC1/SE1 DREFSSCLK 6
19 18 DREFSSCLK#_R 3 4
A1A:(9/24) FAE : (14M_ICH and SIO_14M) signals trace should be equal length VSS_PLL3 SRC1#/SE2 DREFSSCLK# 6
52 VSS_CPU
23 13 DREFCLK_R RP33 3 4 0X2
VSS_SRC1 SRC0/DOT96 DREFCLK 6
29 14 DREFCLK#_R 1 2
A1A:(9/24) ICS FAE suggest R change from 22 to 33 ohm VSS_SRC2 SRC0#/DOT96# DREFCLK# 6
42 VSS_SRC3
A1A:(9/20) change R186 value from 33ohm to 22 ohm(Intel check list 1.301) 58 56
VSS_REF CKPWRGD/PWRDWN# CK_PWRGD 16
ICS9LPRS365AGLFT/ SLG8SP512T During initial power-up be used to
sample FSB speed with FSA/B/C
C2A:(12/26) Base on vendor-FCE suggestion,
change C310/C299 from CH03306JBD7 (33p) to CH02706JB06(27p) C2A:(12/12)change from +1.05V to +1.25V.
Because VDD_IO will drop out when high loading
C310 27P_4 CG_XIN
Clock Gen Differential IO power
(1)PCI2/TME: PU be used, the CK505 cannot over clock any of the clock for Trust Mode security purposes.
2
Y2
(2)PCI4/SRC5_EN: PU be used, the CK505 will be configured to use Pin37/38 to SRC5 clock. +1.25V_VDD +1.25V
14.318MHZ If PD be detect at powe-on,the CK505 will setting Pin 37/38 to PCI_STOP/CUP_SOTP
(Default is setting to PCI_STOP/CUP_SOTP)
1
C299 27P_4 CG_XOUT L26
BKP1608HS181-T_6
(3)PCIF5/ITP_EN: PU be used, the CK505 will be configured to use Pin46/47 to CPU ITP clock.
XTAL length < 500mils If PD be detect at powe-on,the CK505 will setting Pin 46/47 to SRC8 C320 C309 C300 C301 C316 C314 C317 C290 C315 C291 C293
B (Default is setting to SRC8) B
*10U_8 *10U_8 *10U_8 10U_8 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4
(4)SLG8SP512 Pin 6 select Pin 17, 18 output is LCDCLK or 27 M, PD is LCDCLK, PU is 27 M ,
Pin 37, 38 will fixed be use CPU_Stop and PCI_Stop.
0.1U close to each VDD_IO Power pin
(5)SLG505YC64 CK505 Standar parts follow standar setting
CPU Clock select
BSEL Frequency Select Table
R180 0_4 CLK_BSEL0
3 CPU_BSEL0 MCH_BSEL0 6
FSC FSB FSA Frequency
+1.05V_CPU R425 *56_4
0 0 0 266Mhz
R179 *1K_4
0 0 1 133Mhz
R440 0_4 CLK_BSEL1 0 1 1 166Mhz
3 CPU_BSEL1 MCH_BSEL1 6
R439 *0_4 0 1 0 200Mhz
A1A: (9/20) Remove 0ohm
A A
+1.05V_CPU R198 *1K_4 1 1 0 400Mhz
1 1 1 Reserved
R448 0_4 CLK_BSEL2
3 CPU_BSEL2 MCH_BSEL2 6
1 0 1 100Mhz
PROJECT : ZU1
R449 *0_4
1 0 0 333Mhz
Size
Quanta Computer Inc.
Document Number Rev
+1.05V_CPU R447 *1K_4
CLK. GEN./ CK505 3B
C2A: (12/10) no stuff R179,R198,R447 for auto CPU frequence selection (follow ZD1,ZO1)
Date: Tuesday, April 10, 2007 Sheet 2 of 39
5 4 3 2 1
5 4 3 2 1
CPU Thermal monitor
U30A
5 H_A#[16:3]
H_A#3 J4 H1
A[3]# ADS# H_ADS# 5
CPU(HOST)
ADDR GROUP 0
H_A#4 L5 E2
A[4]# BNR# H_BNR# 5 +3V
H_A#5 L4 G5
A[5]# BPRI# H_BPRI# 5
H_A#6 K5
H_A#7 A[6]#
M3 A[7]# DEFER# H5 H_DEFER# 5
H_A#8 N2 F21
A[8]# DRDY# H_DRDY# 5
H_A#9 J1 E1
A[9]# DBSY# H_DBSY# 5
H_A#10 N3
H_A#11 A[10]#
P5 A[11]# BR0# F1 H_BREQ#0 5
H_A#12 P2 A1A:(9/29) change SMBUS from MBCLK/MNDATA to 2ND_MBCLK/2ND_MBDATA
CONTROL
H_A#13 A[12]#
L2 A[13]# IERR# D20 H_IERR# R109 56.2_4 +1.05V_CPU
H_A#14 P4 B3 +3V R388 R387 R385
A[14]# INIT# H_INIT# 14
H_A#15 P1
H_A#16 A[15]# Q31 10K_4 10K_4 200_6
R1 A[16]# LOCK# H4 H_LOCK# 5
2
D RHU002N06 LM86VCC D
5 H_ADSTB0# M1 ADSTB[0]#
5 H_REQ#[4:0] RESET# C1 H_CPURST# 5
H_REQ#0 K3 F3 28 2ND_MBCLK 3 1 C466
REQ[0]# RS[0]# H_RS#0 5
H_REQ#1 H2 F4
REQ[1]# RS[1]# H_RS#1 5
H_REQ#2 K2 G3 .1U_4
REQ[2]# RS[2]# H_RS#2 5
H_REQ#3 J3 G2 +3V
REQ[3]# TRDY# H_TRDY# 5
H_REQ#4 L1 U27
REQ[4]# Q30 H_THERMDA
5 H_A#[35:17] HIT# G6 H_HIT# 5
2
H_A#17 Y2 E4 RHU002N06 8 1
A[17]# HITM# H_HITM# 5 SCLK VCC
H_A#18 U5
H_A#19 A[18]# C461
R3 A[19]# BPM[0]# AD4 28 2ND_MBDATA 3 1 7 SDA DXP 2
ADDR GROUP 1
H_A#20 W6 AD3
H_A#21 A[20]# BPM[1]# A1A: (9/4) +3V 2200P_4
XDP/ITP SIGNALS
U4 A[21]# BPM[2]# AD1 6 ALERT# DXN 3
H_A#22 Y5 AC4 Remove XDP/ITP signals
H_A#23 A[22]# BPM[3]# H_THERMDC
U1 A[23]# PRDY# AC2 4 OVERT# GND 5
H_A#24 R4 AC1 A1A: (9/26) Add (U27/Pin6) PU to 3V R389
H_A#25 A[24]# PREQ# XDP_TCK A1A: (10/30) remove R389, already PU in ICH8
T5 A[25]# TCK AC5
H_A#26 T3 AA6 XDP_TDI *10K_4 MAX6657
A[26]# TDI
H_A#27 W2 A[27]# TDO AB3 16 THERM_ALERT# R390 *0_4 THERM_ALERT#_R ADDRESS: 98H
H_A#28 W5 ◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo