Service Manuals, User Guides, Schematic Diagrams or docs for : acer Acer Aspire 3020_5020_TravelMate_4400_Wistron_Bolsena_RevSA
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5 4 3 2 1
Dummy when use EZ4
Dummy when no EZ4 Bolsena Block Diagram 91.4C501.001 (04243)
Dummy when use 10/100 200-PIN DDR SODIMM
Dummy when use Giga CLK GEN AMD CPU DDR 3 33/400 DDR x2
Dummy when use UMA IDT CV137 3 35W/25W PCB Layer Stackup
D D
Dummy when use Discrete 8,9,10
L1: Signal 1
Dummy when use SATA
17
4,5,6,7 L2: GND
LEDs
Dummy when use IDE L3: Signal 2
SVIDEO/COMP
HyperTransport TVOUT 1 6 L4: Signal 3
6.4GB/S 16b/8b L5: VCC
PWR SW
TSP2220A L6: Signal 4
28
TI LVDS
PCMCIA
SLOT
PCI 7411 ATI LCD 17 ?modify power block
PCMCIA I/F 1* Slot Cardbus
Support 1* 13 94
RS480M Battery Charger 48
TypeII MS/MSpro AGTL+ CPU I/F + UMA
28 PCI Express x16 ATI
SDIO/MMC/SD 1 1,12,13,14 RGB CRT INPUTS OUTPUTS
5 in 1 28
M26/M24 CRT 16
1394 4pin 50,5 1,52 AD+ DCBATOUT
C
Conn 2 8 26, 27 SiI1162 BAT+ C
PCI-Express 15
SYSTEM DC/DC 44
x2 TM DS DVI-D
VRAM x4
HY5DS5 73222F
(EZ4 only ) 1 5 INPUT OUTPUT
53, 54
ATI BlueTooth DCBATOUT 5V_S5 ,
3D3V_S5
SB400 miniUSB
Mini-PCI PCI Bus / 33MHz 24 SYSTEM DC/DC
ACPI 2.0 6xUSB 2.0
USB x 4 45, 46
802.11a/b/g PCI 24
CODEC
31 ALC655 Line In 3 3 INPUT OUTPUT
AC97 MIC In DCBATOUT 2D5V_S3
32 1D8V_S5
6- CH 1D2V_S0
1 0 0 0 Mb AC97 2.2
RJ45 TXFM PCI LAN Line Out
30 30
MODEM RJ11
Realtek OP AMP
MDC Card CONN 33
RTL8110SBL 29 G1421 CPU V_CORE42, 43
24 33
1000/100/10
TXFM 1 0/100Mb Int. SPKR
B
RTL8100C INPUT OUTPUT B
30 33
100/10 29 LPC Bus / 33MHz
LPC I/F DCBATOUT VCC_CORE_S0
ATA 133 18,19,20,21,22 SYSTEM POWER 4 7
Thermal XB US INPUT OUTPUT
NS SIO KBC
& Fan
P IDE
SIDE
PC87392 KB3910
37
G792 2 3 34 2D5V_S3 1D25V_S3
DVD/ DCBATOUT 5V_AUX_S5
SATA HDD
CD-RW
25 25 25
ISA ROM
FIR Touch Int. 36
TF DU6102 Pad KB
37 35 35
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Port Replicator 4 (124 PIN) Taipei Hsien 221, Taiwan, R.O.C.
Title
AC RJ45-11 SEARIAL PRINTER PS2 MIC LINE IN LINE TV DVI PCIeX2 SMBUS BLOCK DIAGRAM
IN PORT CRT OUT OUT Size
A3
Document Number Rev
SA
Bolsena
Date: Tuesday, December 28, 2004 Sheet 1 of 58
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CHANGE HISTORY
Size Document Number Rev
A3 Bolsena SA
Date: Tuesday, December 28, 2004 Sheet 2 of 58
5 4 3 2 1
A B C D E
3D3V_S0
3D3V_S0 3D3V_CLK_VDD 3D3V_CLK_VDDA
1 L12 1 L22
0R3-U 0R3-U
1
1
1
1
1
1
1
C1 C2 C3 C4 C5 C6 C7
SCD1U16V SCD1U16V SCD1U16V SCD1U16V SC22U10V6ZY-U SCD1U16V SC22U10V6ZY-U
2
2
2
2
2
2
2
RN1
2 3 SBLINK_CLK# 13
3D3V_CLK_VDDA 1 4 SBLINK_CLK 13
1 RN2
1
1
1
4 1 SRN33-2-U2
4 SBSRC_CLK# 18 4
C8 C9 C10 C11 3D3V_S0 3D3V_CLK_VDD 2 3 SBSRC_CLK 18
SCD1U16V SCD1U16V SCD1U16V SCD1U16V U1
2
2
2
2
SRN33-2-U2
1 L32 3D3VDD48_S0 3 33 SRC_CLK0# RN3
0R3-U VDD_48 SRCC0 SRC_CLK0
39 VDDA SRCT0 34 1 4 CLK_PCIE_DOCK1# 57
1
32 25 SRC_CLK3# 2 3 CLK_PCIE_DOCK1 57
C12 VDD_SRC SRCC3 SRC_CLK3
SRCT3 24
SC2D2U16V5ZY 21 23 SRC_CLK4# SRN33-2-U2
2
VDD_SRC SRCC4 SRC_CLK4
14 22 RN4
VDD_SRC SRCT4 SRC_CLK5#
35 VDD_SRC SRCC5 19 1 4 CLK_PCIE_DOCK2# 57
18 SRC_CLK5 2 3 CLK_PCIE_DOCK2 57
SRCT5
56 VDD_REF SRCC6 17
51 16 SRN33-2-U2
VDD_PC1 SRCT6
1 2 C13 XI_CLK
SC33P50V2JN
43 VDD_CPU SRCC7 13 Dummy when no EZ4
48 VDD_HTT SRCT7 12
1
2
X1 DY R2 40
DUMMY-R3 CPUC1
1 XIN CPUT1 41
2 44 CPUCLKJ _CY 1 R12 CPUCLK# 6
XOUT CPUC0 CPUCLK_CY 15R2J
R3
X-14D318MHZ-1-U1 45 1 2 CPUCLK 6
1
USB_48M CPUT0 15R2J
4
2
USB_48
1 2 C14 XO_CLK SMBC_CLK 7 SCL
RN5
SC33P50V2JN SMBD_CLK 8 29 ATI_CLK0# 2 3
SDA SRCC1 NBSRC_CLK# 13
1 R4 2 30 ATI_CLK0 1 4 NBSRC_CLK 13
26 CLK48_CARDBUS R5 22R2 SRCT1 ATI_CLK1#
21 CLK48_USB 1 2 10 CLKREQ0# SRCC2 28
1 R7 22R2
2 11 27 ATI_CLK1 SRN33-2-U2
8,21,57 SMBC_SB R6 0R2-0 CLKREQ1# SRCT2
8,21,57 SMBD_SB 1 2
0R2-0 RN6
3 FS2 9 36 1 4 GFX_CLK# 49
3
R9 FS1 SEL24/24_48# VSS_SRC
13 CLK14_NB 1 2 53 REF1 VSS_SRC 20 2 3 GFX_CLK 49
1 R82 33R2 FS0 54 15
21 SB_OSC_CLK 33R2 REF0 RESET#
26 SRN33-2-U2
R10 CLK_REF2 52 TURBO1
37 CLK14_SIO 1 2 REF2
R11 13 HTREF_CLK
33R2
R12 CLK_HTT66 47 VSS_CPU 42 Dummy when use UMA
32 CLK14_AUDIO 1 2 1 2 HTT66 VSS_PCI 49
33R2 33R2 50 46
PCI0 VSS_HTT SBLINK_CLK# R13
VSS_SRC 31 1 2
IREF_CLKGEN 37 38 49D9R2F
IREF VSSA SBLINK_CLK R14
1 VSS_48 5 1 2
1
6 55 49D9R2F
R15 R16 NC#6 VSS_REF SBSRC_CLK# R17
1 2
49D9R2F 475R2F 49D9R2F
IDTCV137PAG SBSRC_CLK 1 R18
2
49D9R2F
2
2
GFX_CLK# 1 R19
2
49D9R2F
GFX_CLK 1 R20
2
49D9R2F
Dummy when use UMA
2 2
NBSRC_CLK# 1 R21
2
49D9R2F
NBSRC_CLK 1 R22
2
49D9R2F
3D3V_CLK_VDD
DY
1 R23
2 FS0
2K2R2
1 R24 2 DY
DUMMY-R2
1 R25
2 DY FS1
2K2R2
1 R26 2 DY
DUMMY-R2
1 1
1 R27
2 DY FS2
2K2R2
1 R28 2 DY Wistron Corporation
DUMMY-R2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CLKGEN_IDTCV137
Size Document Number Rev
A3 SA
Bolsena
Date: Tuesday, December 28, 2004 Sheet 3 of 58
A B C D E
A B C D E
1D2V_HT0A_S0
1
1
1
1
C19 C20 C21 C22
SCD22U16V3ZY SCD22U16V3ZY SCD22U16V3ZY SCD22U16V3ZY
2
2
2
2
4 4
HTT for CPU sideA HTT for CPU sideB
Transmit power Receive power
and NB sideA Receive and NB sideA
power Transmit power
1D2V_HT0A_S0 U2A 1D2V_HT0B_S0
D29 VLDT0_A VLDT0_B AH29 LAYOUT: Place bypass cap on topside of board near
D27 AH27
VLDT0_A VLDT0_B HTT power pins that are not connected directly to
1
D25 VLDT0_A VLDT0_B AG28
3 C28 AG26 C23 downstream HTT device, but connected internally to 3
VLDT0_A VLDT0_B SC4D7U10V5ZY
C26 AF29
other HTT power pins.
2
VLDT0_A VLDT0_B
B29 VLDT0_A VLDT0_B AE28
B27 VLDT0_A VLDT0_B AF25
NB0CADOUT15 T25 N26 CPUCADOUT15 CPUCADOUT[15..0] 11
11 NB0CADOUT[15..0] NB0CADOUTJ15 L0_CADIN_H15 L0_CADOUT_H15 CPUCADOUTJ15
11 NB0CADOUTJ[15..0] R25 L0_CADIN_L15 L0_CADOUT_L15 N27 CPUCADOUTJ[15..0] 11
NB0CADOUT14 U27 L25 CPUCADOUT14
NB0CADOUTJ14 L0_CADIN_H14 L0_CADOUT_H14 CPUCADOUTJ14
U26 L0_CADIN_L14 L0_CADOUT_L14 M25
Used SideB Power Plane NB0CADOUT13 V25 L26 CPUCADOUT13 Used SideA Power Plane
NB0CADOUTJ13 L0_CADIN_H13 L0_CADOUT_H13 CPUCADOUTJ13
U25 L0_CADIN_L13 L0_CADOUT_L13 L27
NB0CADOUT12 W27 J25 CPUCADOUT12
NB0CADOUTJ12 L0_CADIN_H12 L0_CADOUT_H12 CPUCADOUTJ12
W26 L0_CADIN_L12 L0_CADOUT_L12 K25
NB0CADOUT11 AA27 G25 CPUCADOUT11
NB0CADOUTJ11 L0_CADIN_H11 L0_CADOUT_H11 CPUCADOUTJ11
AA26 L0_CADIN_L11 L0_CADOUT_L11 H25
NB0CADOUT10 AB25 G26 CPUCADOUT10
NB0CADOUTJ10 L0_CADIN_H10 L0_CADOUT_H10 CPUCADOUTJ10
AA25 L0_CADIN_L10 L0_CADOUT_L10 G27
NB0CADOUT9 AC27 E25 CPUCADOUT9
NB0CADOUTJ9 L0_CADIN_H9 L0_CADOUT_H9 CPUCADOUTJ9
AC26 L0_CADIN_L9 L0_CADOUT_L9 F25
NB0CADOUT8 AD25 E26 CPUCADOUT8
NB0CADOUTJ8 L0_CADIN_H8 L0_CADOUT_H8 CPUCADOUTJ8
AC25 L0_CADIN_L8 L0_CADOUT_L8 E27
NB0CADOUT7 T27 N29 CPUCADOUT7
NB0CADOUTJ7 L0_CADIN_H7 L0_CADOUT_H7 CPUCADOUTJ7
T28 L0_CADIN_L7 L0_CADOUT_L7 P29
NB0CADOUT6 V29 M28 CPUCADOUT6
NB0CADOUTJ6 L0_CADIN_H6 L0_CADOUT_H6 CPUCADOUTJ6
U29 L0_CADIN_L6 L0_CADOUT_L6 M27
NB0CADOUT5 V27 L29 CPUCADOUT5
NB0CADOUTJ5 L0_CADIN_H5 L0_CADOUT_H5 CPUCADOUTJ5
V28 L0_CADIN_L5 L0_CADOUT_L5 M29
NB0CADOUT4 Y29 K28 CPUCADOUT4
NB0CADOUTJ4 L0_CADIN_H4 L0_CADOUT_H4 CPUCADOUTJ4
W29 L0_CADIN_L4 L0_CADOUT_L4 K27
2 NB0CADOUT3 CPUCADOUT3 2
AB29 L0_CADIN_H3 L0_CADOUT_H3 H28
NB0CADOUTJ3 AA29 H27 CPUCADOUTJ3
NB0CADOUT2 L0_CADIN_L3 L0_CADOUT_L3 CPUCADOUT2
AB27 L0_CADIN_H2 L0_CADOUT_H2 G29
NB0CADOUTJ2 AB28 H29 CPUCADOUTJ2
NB0CADOUT1 L0_CADIN_L2 L0_CADOUT_L2 CPUCADOUT1
AD29 L0_CADIN_H1 L0_CADOUT_H1 F28
NB0CADOUTJ1 AC29 F27 CPUCADOUTJ1
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