Service Manuals, User Guides, Schematic Diagrams or docs for : acer Acer Aspire One AO521 (Quanta ZH9) AMD laptop schematics
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>> Download Acer Aspire One AO521 (Quanta ZH9) AMD laptop schematics documenatation <<
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1 2 3 4 5 6 7 8
ZH9 Block Diagram (AMD Nile Platform)
DDR III,800 MT/s UNBUFFERED
DDRIII SODIMM
HDT
Geneva Channel A P15
P4 AMD ASB2 CPU
A
K125 (Athlon SC) 12W HT1 A
K325 (Athlon DC) 12W HT1
(812 balls ; 27x27mm)
P2~5
HyperTransport LINK
16x16
LVDS MUX
LVDS CON RS880M
P16
HyperTransport LINK0 CPU I/F
TMDS(PCIE 4x1)
HDMI CON DX10 IGP DDRIII SIDE PORT
P17 DDRIII 128MB
SIDE PORT MEMORY P6
DAC
VGA CON LVDS
B
P16 B
1X16 PCIE I/F
PCIE GEN1
1X4 PCIE I/F WITH SB
6X1 PCIE I/F
0
LAN-AR8152L (21x21mm)
P21 P6~9
2 4 A-Link X4
3G
P23
SB820M
1
WLAN/WiMAX
2 USB2.0(14)+1.1(2) HD AUDIO I/F AZALIA CODEC Headphone Jack
P23
SATA III(6 PORTS)
CX20672 P19 MIC In Jack
Digital MIC
4X1 PCIE GEN2 I/F
Speaker Header P19
SIM CARD 8 PCI/PCI BDGE
P23
INT. RTC SATA II I/F
C Mobile 2.5" HDD C
INT. CLK P22
Bluetooth 5
EC
P18
HD AUDIO
LPC I/F
ACPI 1.1
(23x23mm)
1 3 7 6 0 USB 2.0
P10~14
5 IN1 CCD USB PORT USB PORT USB PORT
P16 (Lower Right) P20 (Upper Right) P20 (Left) P20
CARDREADER
P24
LPC
BATTERY CHAGER +1.8V
NB CORE
P26 P29 P32
EC Winbond NPCE781L
om
D D
P25
l.c
SYSTEM DDR 1.5VSUS Discharge/+2.5V/
ai
5V/3V PCU P27 P30 VDDR P33 SMBUS
tm
ho
AMD CPU Core +1.1V Thermal Protection CPU
Keyboard Touch Pad SPI Flash Charger PWM FAN THERMAL SENSOR
f@
CPU_NB Core P28 (VLDT) P31 P34 Quanta Computer Inc.
P18 P18 P25 P26 P4 P4
in
PROJECT : ZH9
xa
Size Document Number Rev
Block Diagram
he
4A
Date: Sunday, March 28, 2010 Sheet 1 of 40
1 2 3 4 5 6 7 8
5 4 3 2 1
D D
U16A
HT_CADINP15 W7 AB6HT_CADOUTP15
HT_CADINN15 L0_CADIN_H15 L0_CADOUT_H15 HT_CADOUTN15
W6 L0_CADIN_L15 L0_CADOUT_L15 AB5
HT_CADINP14 U6 AB9HT_CADOUTP14
HT_CADINN14 L0_CADIN_H14 L0_CADOUT_H14 HT_CADOUTN14
U5 L0_CADIN_L14 L0_CADOUT_L14 AB8
HT_CADINP[15..0] HT_CADINP13 R7 AC7HT_CADOUTP13
<6> HT_CADINP[15..0] L0_CADIN_H13 L0_CADOUT_H13
HT_CADINN13 R6 AC6HT_CADOUTN13
HT_CADINN[15..0] HT_CADINP12 L0_CADIN_L13 L0_CADOUT_L13 HT_CADOUTP12
<6> HT_CADINN[15..0] P6 L0_CADIN_H12 L0_CADOUT_H12 AE6
HT_CADINN12 P5 AE5HT_CADOUTN12
HT_CLKINP[1..0] HT_CADINP11 L0_CADIN_L12 L0_CADOUT_L12 HT_CADOUTP11
<6> HT_CLKINP[1..0] L6 L0_CADIN_H11 L0_CADOUT_H11 AE9
HT_CADINN11 L5 AE8HT_CADOUTN11
HT_CLKINN[1..0] HT_CADINP10 L0_CADIN_L11 L0_CADOUT_L11 HT_CADOUTP10
<6> HT_CLKINN[1..0] J6 L0_CADIN_H10 L0_CADOUT_H10 AH3
C HT_CADINN10 J5 AH4HT_CADOUTN10 C
HT_CTLINP[1..0] HT_CADINP9 L0_CADIN_L10 L0_CADOUT_L10 HT_CADOUTP9
<6> HT_CTLINP[1..0] H4 L0_CADIN_H9 L0_CADOUT_H9 AK3
HT_CADINN9 H3 AK4HT_CADOUTN9
HT_CTLINN[1..0] HT_CADINP8 L0_CADIN_L9 L0_CADOUT_L9 HT_CADOUTP8
<6> HT_CTLINN[1..0] G6 L0_CADIN_H8 L0_CADOUT_H8 AH1
HT_CADINN8 G5 AH2HT_CADOUTN8
HT_CADOUTP[15..0] HT_CADINP7 L0_CADIN_L8 L0_CADOUT_L8
Y1 HT_CADOUTP7
HT LINK
<6> HT_CADOUTP[15..0] T3 L0_CADIN_H7 L0_CADOUT_H7
HT_CADINN7 T4 Y2 HT_CADOUTN7
HT_CADOUTN[15..0] HT_CADINP6 L0_CADIN_L7 L0_CADOUT_L7
<6> HT_CADOUTN[15..0] T2 L0_CADIN_H6 L0_CADOUT_H6 Y4 HT_CADOUTP6
HT_CADINN6 T1 Y3 HT_CADOUTN6
HT_CLKOUTP[1..0] HT_CADINP5 L0_CADIN_L6 L0_CADOUT_L6 HT_CADOUTP5
<6> HT_CLKOUTP[1..0] P3 L0_CADIN_H5 L0_CADOUT_H5 AB1
HT_CADINN5 P4 AB2HT_CADOUTN5
HT_CLKOUTN[1..0] HT_CADINP4 L0_CADIN_L5 L0_CADOUT_L5 HT_CADOUTP4
<6> HT_CLKOUTN[1..0] P2 L0_CADIN_H4 L0_CADOUT_H4 AB4
HT_CADINN4 P1 AB3HT_CADOUTN4
HT_CTLOUTP[1..0] HT_CADINP3 L0_CADIN_L4 L0_CADOUT_L4 HT_CADOUTP3
<6> HT_CTLOUTP[1..0] M2 L0_CADIN_H3 L0_CADOUT_H3 AD4
HT_CADINN3 M1 AD3HT_CADOUTN3
HT_CTLOUTN[1..0] HT_CADINP2 L0_CADIN_L3 L0_CADOUT_L3
<6> HT_CTLOUTN[1..0] K3 L0_CADIN_H2 L0_CADOUT_H2 AF1HT_CADOUTP2
HT_CADINN2 K4 AF2HT_CADOUTN2
HT_CADINP1 L0_CADIN_L2 L0_CADOUT_L2
K2 L0_CADIN_H1 L0_CADOUT_H1 AF4HT_CADOUTP1
HT_CADINN1 K1 AF3HT_CADOUTN1
HT_CADINP0 L0_CADIN_L1 L0_CADOUT_L1 HT_CADOUTP0
H2 L0_CADIN_H0 L0_CADOUT_H0 AK1
HT_CADINN0 H1 AK2HT_CADOUTN0
L0_CADIN_L0 L0_CADOUT_L0
B HT_CLKINP1 B
M8 L0_CLKIN_H1 L0_CLKOUT_H1 AF6HT_CLKOUTP1
HT_CLKINN1 M7 AF5HT_CLKOUTN1
L0_CLKIN_L1 L0_CLKOUT_L1
HT_CLKINP0 M3 AD1HT_CLKOUTP0
HT_CLKINN0 L0_CLKIN_H0 L0_CLKOUT_H0 HT_CLKOUTN0
M4 L0_CLKIN_L0 L0_CLKOUT_L0 AD2
HT_CTLINP1 Y6 Y8 HT_CTLOUTP1
HT_CTLINN1 L0_CTLIN_H1 L0_CTLOUT_H1
Y5 L0_CTLIN_L1 L0_CTLOUT_L1 Y9 HT_CTLOUTN1
HT_CTLINP0 V2 V4 HT_CTLOUTP0
HT_CTLINN0 L0_CTLIN_H0 L0_CTLOUT_H0
V1 L0_CTLIN_L0 L0_CTLOUT_L0 V3 HT_CTLOUTN0
A A
Quanta Computer Inc.
PROJECT : ZH9
Size Document Number Rev
ASB2 HT I/F 1/4 4A
Date: Sunday, March 28, 2010 Sheet 2 of 40
5 4 3 2 1
A B C D E
Processor Memory Interface
U16B U16C
<15> M_A_A[0..15] M_A_DQ[0..63] <15>
M_A_A15 P30 M_A_DQ63
AG11 P33 AN13
M_A_A14 M29 MA_ADD15 MA_DATA63 M_A_DQ62 MB_ADD15 MB_DATA63
MA_ADD14 MA_DATA62 AH11 P31 MB_ADD14 MB_DATA62 AL14
M_A_A13AG28 M_A_DQ61
AJ12 AJ33 AL16
M_A_A12 P28 MA_ADD13 MA_DATA61 M_A_DQ60 MB_ADD13 MB_DATA61
MA_ADD12 MA_DATA60 AJ14 T32 MB_ADD12 MB_DATA60 AN17
M_A_A11 T30 M_A_DQ59
AF11 T31 AN12
M_A_A10AC28 MA_ADD11 MA_DATA59 M_A_DQ58 MB_ADD11 MB_DATA59
4 MA_ADD10 MA_DATA58 AF12 AD32 MB_ADD10 MB_DATA58 AM12 4
M_A_A9 P27 M_A_DQ57
AG12 T33 AM16
M_A_A8 R26 MA_ADD9 MA_DATA57 M_A_DQ56 MB_ADD9 MB_DATA57
MA_ADD8 MA_DATA56 AH12 V32 MB_ADD8 MB_DATA56 AN16
M_A_A7 R27 M_A_DQ55
AK14 U33 AL18
M_A_A6 U28 MA_ADD7 MA_DATA55 M_A_DQ54 MB_ADD7 MB_DATA55
MA_ADD6 MA_DATA54 AF15 V33 MB_ADD6 MB_DATA54 AN19
M_A_A5 V30 M_A_DQ53
AH19 V31 AM24
M_A_A4 U27 MA_ADD5 MA_DATA53 M_A_DQ52 MB_ADD5 MB_DATA53
MA_ADD4 MA_DATA52 AK20 W33 MB_ADD4 MB_DATA52 AN24
M_A_A3 Y30 M_A_DQ51
AF14 Y31 AM18
M_A_A2 AB29 MA_ADD3 MA_DATA51 M_A_DQ50 MB_ADD3 MB_DATA51
MA_ADD2 MA_DATA50 AG14 Y33 MB_ADD2 MB_DATA50 AN18
M_A_A1 W29 M_A_DQ49
AF17 Y32 AL22
M_A_A0 AC26 MA_ADD1 MA_DATA49 M_A_DQ48 MB_ADD1 MB_DATA49
MA_ADD0 MA_DATA48 AG19 AC33 MB_ADD0 MB_DATA48 AN23
M_A_DQ47
AG20 AM25
MA_DATA47 M_A_DQ46 MB_DATA47
<15> M_A_BANK2 R29 MA_BANK2 MA_DATA46 AJ20 R33 MB_BANK2 MB_DATA46 AL26
AC29 M_A_DQ45
AF22 AD33 AN28
<15> M_A_BANK1 MA_BANK1 MA_DATA45 MB_BANK1 MB_DATA45
AE28 M_A_DQ44
AK24 AE33 AL28
<15> M_A_BANK0 MA_BANK0 MA_DATA44 MB_BANK0 MB_DATA44
M_A_DQ43
AF19 AL24
MA_DATA43 M_A_DQ42 MB_DATA43
K30 MA_CHECK7 MA_DATA42 AF20 K33 MB_CHECK7 MB_DATA42 AN25
J29 M_A_DQ41
AJ23 K31 AN27
MA_CHECK6 MA_DATA41 M_A_DQ40 MB_CHECK6 MB_DATA41
G29 MA_CHECK5 MA_DATA40 AG23 G32 MB_CHECK5 MB_DATA40 AM28
F29 M_A_DQ39
AF23 F32 AM29
MA_CHECK4 MA_DATA39 M_A_DQ38 MB_CHECK4 MB_DATA39
L28 MA_CHECK3 MA_DATA38 AF25 L33 MB_CHECK3 MB_DATA38 AL30
L29 M_A_DQ37
AH27 K32 AL32
MA_CHECK2 MA_DATA37 M_A_DQ36 MB_CHECK2 MB_DATA37
H29 MA_CHECK1 MA_DATA36 AK30 H31 MB_CHECK1 MB_DATA36 AL33
H27 M_A_DQ35
AJ25 G33 AK28
MA_CHECK0 MA_DATA35 M_A_DQ34 MB_CHECK0 MB_DATA35
MA_DATA34 AG25 MB_DATA34 AN29
J27 M_A_DQ33
AJ26 J33 AM31
MA_DQS_H8 MA_DATA33 MB_DQS_H8 MB_DATA33
DDR III: CHANNEL A
J26 M_A_DQ32
AJ28 H32 AM32
MA_DQS_L8 MA_DATA32 MB_DQS_L8 MB_DATA32
DDR III: CHANNEL B
3 AJ11 D28M_A_DQ31 AM14 E33 3
<15> M_A_DQSP7 MA_DQS_H7 MA_DATA31 MB_DQS_H7 MB_DATA31
AK12 G28M_A_DQ30 AN14 D31
<15> M_A_DQSN7 MA_DQS_L7 MA_DATA30 MB_DQS_L7 MB_DATA30
AG15 D26M_A_DQ29 AL20 B31
<15> M_A_DQSP6 MA_DQS_H6 MA_DATA29 MB_DQS_H6 MB_DATA29
<15> M_A_DQSN6 AH15 MA_DQS_L6 MA_DATA28 E26M_A_DQ28 AM20 MB_DQS_L6 MB_DATA28 A31
<15> M_A_DQSP5 AH22 MA_DQS_H5 MA_DATA27 F30M_A_DQ27 AN26 MB_DQS_H5 MB_DATA27 F33
<15> M_A_DQSN5 AG22 MA_DQS_L5 MA_DATA26 E29M_A_DQ26 AM26 MB_DQS_L5 MB_DATA26 F31
<15> M_A_DQSP4 AG26 MA_DQS_H4 MA_DATA25 F27M_A_DQ25 AN30 MB_DQS_H4 MB_DATA25 C32
AH26 H26M_A_DQ24 AM30 B32
<15> M_A_DQSN4 MA_DQS_L4 MA_DATA24 MB_DQS_L4 MB_DATA24
E28 H25M_A_DQ23 D33 C30
<15> M_A_DQSP3 MA_DQS_H3 MA_DATA23 MB_DQS_H3 MB_DATA23
F28 D24M_A_DQ22 D32 A29
<15> M_A_DQSN3 MA_DQS_L3 MA_DATA22 MB_DQS_L3 MB_DATA22
E25 H22M_A_DQ21 B28 B26
<15> M_A_DQSP2 MA_DQS_H2 MA_DATA21 MB_DQS_H2 MB_DATA21
<15> M_A_DQSN2 F25 MA_DQS_L2 MA_DATA20 E22M_A_DQ20 A28 MB_DQS_L2 MB_DATA20 A26
<15> M_A_DQSP1 G17 MA_DQS_H1 MA_DATA19 F26M_A_DQ19 A21 MB_DQS_H1 MB_DATA19 B30
H17 G26M_A_DQ18 B20 A30
<15> M_A_DQSN1 MA_DQS_L1 MA_DATA18 MB_DQS_L1 MB_DATA18
E12 D22M_A_DQ17 B16 A27
<15> M_A_DQSP0 MA_DQS_H0 MA_DATA17 MB_DQS_H0 MB_DATA17
F12 G23M_A_DQ16 A15 C26
<15> M_A_DQSN0 MA_DQS_L0 MA_DATA16 MB_DQS_L0 MB_DATA16
G22M_A_DQ15 A24
MA_DATA15 M_A_DQ14 MB_DATA15
AK18 MA_CLK_H7 MA_DATA14 G20 AN22 MB_CLK_H7 MB_DATA14 B24
AJ17 G15M_A_DQ13 AM22 C18
MA_CLK_L7 MA_DATA13 MB_CLK_L7 MB_DATA13
AH17 MA_CLK_H6 MA_DATA12 F15M_A_DQ12 AN21 MB_CLK_H6 MB_DATA12 A18
AG17 D20M_A_DQ11 AM21 A25
MA_CLK_L6 MA_DATA11 MB_CLK_L6 MB_DATA11
<15> M_A_CLKP1 Y28 MA_CLK_H5 MA_DATA10 F22M_A_DQ10 AA32 MB_CLK_H5 MB_DATA10 C24
Y27 D16M_A_DQ9 AA33 C20
<15> M_A_CLKN1 MA_CLK_L5 MA_DATA9 MB_CLK_L5 MB_DATA9
<15> M_A_CLKP2 AB27 MA_CLK_H4 MA_DATA8 E17M_A_DQ8 AB33 MB_CLK_H4 MB_DATA8 A19
AB26 H15M_A_DQ7 AB32 C16
<15> M_A_CLKN2 MA_CLK_L4 MA_DATA7 MB_CLK_L4 MB_DATA7
W27 H14M_A_DQ6 AB31 A16
MA_CLK_H3 MA_DATA6 M_A_DQ5 MB_CLK_H3 MB_DATA6
W26 MA_CLK_L3 MA_DATA5 G12 AB30 MB_CLK_L3 MB_DATA5 B14
2 P26 H12M_A_DQ4 AD31 A13 2
MA_CLK_H2 MA_DATA4 MB_CLK_H2 MB_DATA4
M26 MA_CLK_L2 MA_DATA3 E15M_A_DQ3 AD30 MB_CLK_L2 MB_DATA3 B18
D18 MA_CLK_H1 MA_DATA2 E14M_A_DQ2 C22 MB_CLK_H1 MB_DATA2 A17
F19 MA_CLK_L1 MA_DATA1 E11M_A_DQ1 B22 MB_CLK_L1 MB_DATA1 C14
E20 MA_CLK_H0 MA_DATA0 F11M_A_DQ0 A22 MB_CLK_H0 MB_DATA0 A14
E19 MA_CLK_L0 A23 MB_CLK_L0
MA_DM8 H30 M_A_DM[0..7] <15> MB_DM8 H33
M30 AL12M_A_DM7 N33 AN15
<15> M_A_CKE1 MA_CKE1 MA_DM7 MB_CKE1 MB_DM7
M28 AK16M_A_DM6 P32 AN20
<15> M_A_CKE0 MA_CKE0 MA_DM6 MB_CKE0 MB_DM6
AK22M_A_DM5 AK26
MA_DM5 M_A_DM4 MB_DM5
AJ29 MA1_ODT1 MA_DM4 AJ27 AK31 MB1_ODT1 MB_DM4 AN31
AF27 MA1_ODT0 MA_DM3 E27 M_A_DM3 AH31 MB1_ODT0 MB_DM3 C33
<15> M_A_ODT1 AJ30 MA0_ODT1 MA_DM2 E23 M_A_DM2 AK32 MB0_ODT1 MB_DM2 C28
<15> M_A_ODT0 AG29 MA0_ODT0 MA_DM1 H19 M_A_DM1 AH33 MB0_ODT0 MB_DM1 A20
MA_DM0 G14 M_A_DM0 MB_DM0 D14
AH29 MA1_CS_L1 AK33 MB1_CS_L1
AE29 MA1_CS_L0 AF33 MB1_CS_L0
<15> M_A_CS#1 AH30 MA0_CS_L1 AJ32 MB0_CS_L1
<15> M_A_CS#0 AF29 MA0_CS_L0 AF31 MB0_CS_L0
<15> M_A_RAS# AC27 MA_RAS_L AF32 MB_RAS_L
<15> M_A_CAS# AF30 MA_CAS_L AH32 MB_CAS_L
<15> M_A_WE# AE27 MA_WE_L AG33 MB_WE_L
<15> M_A_RST# L27 MA_RESET_L L32 MB_RESET_L
R285 *0/J_4M32 M33
om
<15> MEMHOT_MA# FREE|MA_EVENT_L FREE|MB_EVENT_L
l.c
1 1
ai
BOM@ASB2_CPU BOM@ASB2_CPU
tm
Route as 60 ohms with V105 : AJ00105VT00
ho
5/10 W/S from CPU pins. K125 : AJ0K125VT02 Quanta Computer Inc.
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K325 : AJ0K325VT02
PROJECT : ZH9
in
K625 : AJ0K625VT03
xa
Size Document Number Rev
ASB2 DDRIII MEMORY 2/4 4A
he
Date: Sunday, March 28, 2010 Sheet 3 of 40
A B C D E
5 4 3 2 1
CPU Thermal monitor(THM) +3V Keep net PWRGD, LDT_STOP#, LDT_RST# no stub
<20100303(C3A)> L37 3A/30ohm_6 CPU_LDT_RST# R309 300/J_4
Reserve R266,C315,C316,U15,R276,R410 and stuff R51~R53,R48,Q7~Q9,D2,D3,R411, for AMD SB-TSI. +CPUVDDA
W/S= 15 mil/20mil CPU_PWRGD R319 300/J_4
+2.5V
CPU_LDT_STOP# R308 300/J_4 +1.5V
R266 DCR:0.03ohm
*200/J_4 C372 C361 C351 C345
180P/50V_4 4.7U/6.3V_6 0.22U/6.3V_4 3300P/50V_4
<20091029(A1A)_47337_ASB2_scl_nda_1.00>
CPU_PRESENT_L net are pulled up to VDDIO with 1Kohm
CPU_TEST20_SCANCLK2 and CPU_TEST21_SCANEN net are pulled down to GND with 1Kohm
+3V_THMVCC
<25> 2ND_MBCLK C315
250mA CPU_PRESENT_L R268 1K/J_4 +1.5VSUS
<25> 2ND_MBDATA ◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo