Service Manuals, User Guides, Schematic Diagrams or docs for : acer Acer Extenza 5430_5530_5530G_Wistron_Olan_RevSA
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5 4 3 2 1
Olan (TM15") Block Diagram Project code: 91.4Z701.001
PCB P/N : 48.4Z701.0SA
REVISION : 07249-SA
PCB STACKUP
DDR2 667/800MHz
TOP
SYSTEM DC/DC
AMD Giffin CPU TPS51125 51
D 667/800 MHz
8,9 G792 INPUTS OUTPUTS
D
VCC
S1G2 (35W) 25 45,46 DCBATOUT
5V_S5(7A)
DDR2 667/800MHz
638-Pin uFCPGA638
4,5,6,7
S 3D3V_S5(7A)
667/800 MHz S SYSTEM DC/DC
8,9 CRT CRT GND TPS51124 52
18 INPUTS OUTPUTS
OUT
BOTTOM 1D1V_S0(9A)
IN
16X16 DCBATOUT
LCD 1D2V_S0(5A)
16
SYSTEM DC/DC
North Bridge HDMI TPS51117 53
CLK GEN. AMD RS780M 19
DVI INPUTS OUTPUTS
Port Replicator
SILEGO SLG8SP628 CPU I/F LVDS, CRT I/F
3 DCBATOUT 1D8V_S3(10A)
INTEGRATED GRAHPICS PCIex16
VGA Borad RT9026PFP 54
DDR_VREF_S3
C 5V_S5 C
11,12,13 37 0D9V_S3
RT9166 54
Line In LAN
A-Link Giga LAN TXFM RJ45 RJ45 3D3V_S0 2D5V_S0
Codec 36 36 (300mA)
42 AZALIA 4X4 BCM5764M 35
G957 54
CX20561
40 New card PWR SW 3D3V_S0 1D5V_S0
(1A)
MIC In 38 TPS223138
South Bridge G9161 54
42 AMD SB700 PCIex1
Mini Card 3D3V_S5 1D2V_S5
Kedron a/b/g/n 39 (400mA)
USB 2.0/1.1 ports
ETHERNET (10/100/1000Mb) CHARGER
42 BQ24745 55
High Definition Audio MS/MS Pro/xD
Line Out ATA 66/100 /MMC/SD/SD IO INPUTS OUTPUTS
Cardbus 5 in 1
33
B (No-SPDIF) PCMCIA CHG_PWR
B
ACPI 1.1 PCI OZ711MZ
32 SLOT 34 18V 6.0A
LPC I/F DCBATOUT
OP AMP UP+5V
42 5V 100mA
APA2031 PCI/PCI BRIDGE
41 20,21,22,23,24 LPC BUS
INT.SPKR CPU DC/DC
USBX4 ISL6265HR 50
USB INPUTS OUTPUTS
MODEM BIOS HP OUT
RJ11 MDC Card SATA KBC Winbond
W25X80
LPC MIC IN VCC_CORE_S0_0
29 Winbond 44 LINE IN 0~1.55V 18A
Mini USB Camera DEBUG
WPC775 CONN.44 VCC_CORE_S0_1
Blue Tooth 28 43 DCBATOUT
0~1.55V 18A
HDD SATA Launch
27 Buttom VDDNB
15 0~1.55V 18A
Finger USB
ODD SATA Printer 31 4 Port 30 Touch INT.
A 26 Pad 43 KB 43 DIS A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
BLOCK DIAGRAM
Size Document Number Rev
A3 SA
Olan
Date: Monday, November 19, 2007 Sheet 1 of 57
5 4 3 2 1
5 4 3 2 1
DATE VERSON ITEM PAGE Modify List Issue Description OWNER
1
2
3
4
5
D D
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C 20 C
21
22
23
24
25
26
27
28
29
30
31
32
33
B
34 B
35
36
37
38
39
40
41
42
43
44
45
46
47
48
A DIS A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
HISTORY
Size Document Number Rev
A3 SA
Olan
Date: Monday, November 19, 2007 Sheet 2 of 57
5 4 3 2 1
5 4 3 2 1
3D3V_S0 3D3V_CLK_VDD
R173 3D3V_S0
R174
1 2
0R3-0-U-GP 1 2 3D3V_48MPWR_S0
1
1
1
1
1
1
1
1
1
C337 C315 C320 C318 C321 C329 C343 C347 C333
SC4D7U6D3V3KX-GP
Due to PLL issue on current clock chip, the SBlink clock
1
1
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C348 C342
2D2R3J-2-GP SC1U10V2KX-1GP need to come from SRC clocks for RS740 and RS780.
DY
2
2
2
2
2
2
2
2
2
Future clock chip revision will fix this.
2
2
3000mA.80ohm
D D
Clock chip has internal serial terminations
3D3V_S0 for differencial pairs, external resistors are
R139 reserved for debug purpose.
1 DY 2
0R3-0-U-GP
1D1V_S0 1D1V_CLK_VDDIO
R145 C340
1 2 R171 SC27P50V2JN-2-GP
0R3-0-U-GP 1 DY 2 2 1
1
1
1
1
1
1
1
C317 C314 C344 C322 C341 C336 C319 3D3V_CLK_VDD X2
1
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
10MR2J-L-GP X-14D31818M-35GP
U18 82.30005.891
2
2
2
2
2
2
2
1D1V_CLK_VDDIO 2ND = 82.30005.951
26 61 GEN_XTAL_IN C346
2
VDDATIG X1 GEN_XTAL_OUT
25 VDDATIG_IO X2 62 2 1
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