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A B C D E
1 1
2
Compal Confidential 2
DCL53 Schematics Document
Banias uFCBGA/uFCPGA Package with Montara-GM
Core Logic
3
2003-06-12 3
REV: 1.0
4 4
Compal Electronics, Inc.
Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DCL53 LA-1881 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, August 11, 2003 Sheet 1 of 40
A B C D E
A B C D E
Compal confidential Block Diagram
Model Name :DCL53
File Name : LA-1881 Rev: 1.0 Mobile Banias Thermal Sensor Clock Generator
1
uFCBGA/uFCPGA CPU ADM1032 ICS950810CG 1
478 pin page 4,5
page 4 page 13
HA#(3..31) HD#(0..63)
Fan Control System Bus
page 31 400MHz
Memory
LVDS & CRT BUS(DDR)
Montara-GM/GM+ DDR-SO-DIMM X2
Connector page 19 2.5V 200MHz/266MHz
BANK 0, 1, 2, 3
DVO uFCBGA-732 pin page 10,11,12
TV-Out Conn. TV Encoder
page 6,7,8,9
page 18 CH7011 page 18
2 HUB-Link 2
USB port 0, 2, 4 USBx3
PCI BUS MBC Conn.
3.3V 33MHz 3.3V 48MHz
USB conn page 25
ICH4-M page 26
USB port 1
MINI 13 94 LAN BGA-421 3.3V 24.576MHz AC-LINK
Controller
CardBus
PCI I/F RTL 8101L ENE CB1410 page 14,15,16
3.3V ATA100
VIA VT6301S
page 24 page 23 page 22 page 20
1394
RJ45 Slot 0 LPC BUS
3
Connector page 22 page 21 3
page 23 3.3V 33MHz
LED INDICATE
Winbond
page 26 NS PC87591L W83L518D 25
LPC to X-BUS page
& KBC HDD CDROM AC97
Power On/Off Codec
SIO LPC47N227 page 29 SD/MS Slot
Reset & RTC page 25
page 17 page 17
ALC202
page 32
page 31
page 27
DC/DC Interface AMP& Phone
Suspend PARALLEL SERIAL Jack
EC I/O Buffer Touch Pad
page 28 page 30 page 28 page 33
page 34
4 4
FIR BIOS Int.KBD
page 30 page 28
Power Circuit
DC/DC
page Compal Electronics, Inc.
36,37,38,39,40,41,42,43
Legacy I/O Option Title
Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DCL53 LA-1881 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, August 11, 2003 Sheet 2 of 40
A B C D E
5 4 3 2 1
H_RS#[0..2] HD#[0..63]
H_RS#[0..2] 5 HD#[0..63] 5
+3VS
HA#[3..31]
5 HA#[3..31]
H_REQ#[0..4]
5 H_REQ#[0..4]
JP12A 1
1
HA#3 P4 A19 HD#0 C103
HA#4
HA#5
U4
A3#
A4#
Banias D0#
D1# A25 HD#1
HD#2 2
0.1U_0402_16V4Z R87
@10K_0402_5%
V3 A5# D2# A22
HA#6 R3 B21 HD#3 1 C100
HA#7 A6# D3# HD#4 2200P_0402_50V7K
V2 A24
2
HA#8 A7# D4# HD#5 U18
D W1 A8# D5# B26 D
HA#9 T4 A21 HD#6 THERMDA 2 1
+VCCP HA#10 A9# D6# HD#7 2 D+ VDD1
W2 A10# D7# B20
HA#11 Y4 C20 HD#8 THERMDC 3 6
HA#12 A11# D8# HD#9 D- ALERT#
Y1 A12# D9# B24
1 R275
2 ITP_TDI HA#13 U1 D24 HD#10 8 4
A13# D10# 27 EC_SMB_CK2 SCLK THERM#
150_0402_5% HA#14 AA3 E24 HD#11
HA#15 A14# D11# HD#12
Y3 A15# D12# C26 27 EC_SMB_DA2 7 SDATA GND 5
1 R278
2 ITP_TRST# HA#16 AA2 B23 HD#13
680_0402_5% HA#17 A16# D13# HD#14
AF4 A17# D14# E23
HA#18 AC4 C25 HD#15 ADM1032ARM_RM8
HA#19 A18# D15# HD#16
AC7 A19# D16# H23
HA#20 AC3 G25 HD#17
HA#21 A20# D17# HD#18
AD3 A21# D18# L23
Note: HA#22 AE4 M26 HD#19
HA#23 A22# D19# HD#20
Placement near to CPU Conn AD2 A23# D20# H24
HA#24 AB4 F25 HD#21
HA#25 A24# D21# HD#22
AC6 A25# ADDR GROUP DATA GROUP D22# G24
HA#26 AD5 J23 HD#23
HA#27 A26# D23# HD#24
AE2 A27# D24# M23
HA#28 AD6 J25 HD#25
HA#29 A28# D25# HD#26
AF3 A29# D26# L26
HA#30 AE1 N24 HD#27
HA#31 A30# D27# HD#28
AF1 A31# D28# M25
H26 HD#29
H_REQ#0 D29# HD#30
R2 REQ0# D30# N25
H_REQ#1 P3 K25 HD#31
H_REQ#2 REQ1# D31# HD#32
T2 REQ2# D32# Y26
H_REQ#3 P1 AA24 HD#33
C H_REQ#4 REQ3# D33# HD#34 C
T1 REQ4# D34# T25
U23 HD#35
D35# HD#36
5 H_ADSTB#0 U3 ADSTB0# D36# V23
AE5 R24 HD#37
5 H_ADSTB#1 ADSTB1# D37#
R26 HD#38
D38# HD#39
D39# R23
A16 AA23 HD#40
12 CLK_CPU_ITP ITP_CLK0 D40#
A15 U26 HD#41
12 CLK_CPU_ITP# ITP_CLK1 D41#
V24 HD#42
D42# HD#43
12 CLK_CPU_BCLK B15 BCLK0 D43# U25
B14 HOST CLK V26 HD#44
12 CLK_CPU_BCLK# BCLK1 D44#
Y23 HD#45
D45# HD#46
D46# AA26
Y25 HD#47 +VCCP
D47# HD#48
5 H_ADS# N2 ADS# D48# AB25
L1 AC23 HD#49
5 H_BNR# BNR# D49#
J3 AB24 HD#50 1 2 ITP_TDO
5 H_BPRI# BPRI# D50# HD#51 R286 @54.9_0402_1%
5 H_BR0# N4 BR0# D51# AC20
L4 AC22 HD#52 1 2 H_CPURST#
5 H_DEFER# DEFER# D52# HD#53 R277 @54.9_0402_1%
5 H_DRDY# H2 DRDY# D53# AC25
K3 AD23 HD#54 1 2 ITP_TMS
5 H_HIT# HIT# D54#
K4 CONTROL GROUP AE22 HD#55 R272 39.2_0603_1%
5 H_HITM# HITM# D55#
1 2 H_IERR# A4 AF23 HD#56
+VCCP R285 IERR# D56# HD#57 ITP_TCK
5 H_LOCK# J2 LOCK# D57# AD24 1 2
56_0402_5% H_CPURST# B11 AF20 HD#58 R287 27.4_0402_1%
5 H_CPURST# RESET# D58# HD#59
D59# AE21
AD21 HD#60
H_RS#0 D60# HD#61
H1 RS0# D61# AF25
H_RS#1 K1 AF22 HD#62 Note:
B H_RS#2 RS1# D62# HD#63 B
L2 RS2# D63# AF26 Placement near to ITP Conn
5 H_TRDY# M3 TRDY#
DINV0# D25 H_DINV#0 5
DINV1# J26 H_DINV#1 5
C8 BPM0# DINV2# T24 H_DINV#2 5
R297 B8 AD20
BPM1# DINV3# H_DINV#3 5
150_0402_5% A9 BPM2#
+3VALW 1 2 C9 BPM3#
DSTBN0# C23 H_DSTBN#0 5
ITP_DBRESET# 1 2 A7 K24
14 ITP_DBRESET# DBR# DSTBN1# H_DSTBN#1 5
R284 0_0402_5% M2 W25
5 H_DBSY# DBSY# DSTBN2# H_DSTBN#2 5
6,13 H_DPSLP# B7 DPSLP# DSTBN3# AE24 H_DSTBN#3 5
6 H_DPWR# C19 DPWR# DSTBP0# C22 H_DSTBP#0 5
A10 PRDY# DSTBP1# L24 H_DSTBP#1 5
+VCCP 1 2 B10 PREQ# MISC DSTBP2# W24 H_DSTBP#2 5
R270 PRO_CHOT#B17 AE25 +3VS
PROCHOT# DSTBP3# H_DSTBP#3 5
330_0402_5%
13 H_PW RGD E4 PWRGOOD
2
13 H_CPUSLP# A6 SLP#
ITP_TCK A13 R309
R274 ITP_TDI TCK 10K_0402_5%
C12 TDI
@1K_0402_5% ITP_TDO A12 C2
TDO A20M# H_A20M# 13
1 2 TEST1 C5 D3 H_FERR# 13
1
TEST2 TEST1 FERR#
1 2 F23 TEST2 IGNNE# A3 H_IGNNE# 13 PROCHOT# 27
R266 ITP_TMS C11 B5
TMS INIT# H_INIT# 13
@1K_0402_5% ITP_TRST# B13 D1
TRST# LINT0 H_INTR 13
1
D4 C
LINT1 H_NMI 13
A LEGACY CPU 1 2 2 Q42 A
+VCCP R282 B
THERMAL STPCLK# C6 H_STPCLK# 13 2SC2411K_SOT23
THERMDA B18 B4 56_0402_5% E
THERMDA DIODE H_SMI# 13
3
THERMDC A18 SMI#
THERMDC
14 THERMTRIP# C17 THERMTRIP# +VCCP 1 2 PRO_CHOT#
R281
56_0402_5%
AMP_1473129-1 Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Banias Processor in mFCPGA479 with ITP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A3 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DCL53 LA-1881
Date: Monday, August 11, 2003 Sheet 3 of 40
5 4 3 2 1
5 4 3 2 1
+CPU_CORE
+CPU_CORE
JP12C
1 1 1 1 1 1
F20 VCC VSS T26
JP12B + C249 + C248 + C251 + C250 + C247 + C246 F22 U2
VCC VSS
G5 VCC VSS U6
1 2 VCCSENSE AE7 A2 G21 U22
R195 VSSSENSE AF6
@54.9_0402_1% VCCSENSE VSS 2 2 2 2 2 2 VCC VSS
1 2 VSSSENSE VSS A5 H6 VCC VSS U24
R188 @54.9_0402_1% A8 220U_D2_4VM_R12 220U_D2_4VM_R12 @220U_D2_4VM_R12 H22 V1
VSS 220U_D2_4VM_R12 220U_D2_4VM_R12 @220U_D2_4VM_R12 VCC VSS
VSS A11 J5 VCC VSS V4
+1.8VS F26 VCCA0 VSS A14 J21 VCC VSS V5
D B1 VCCA1 VSS A17 K22 VCC VSS V21 D
N1 A20 +CPU_CORE U5 V25
VCCA2 VSS VCC VSS
AC26 VCCA3 VSS A23 V6 VCC VSS W3
VSS A26 V22 VCC VSS W6
+VCCP P23 VCCQ0 VSS B3 1 1 1 1 1 1 1 W5 VCC VSS W22
W4 VCCQ1 VSS B6 W21 VCC VSS W23
B9 C266 C318 C264 C355 C324 C314 C356 Y6 W26
VSS
B12 Y22
VCC Banias VSS
Y2
D10 VCCP
Banias VSS
VSS B16
2 2
10U_0805_6.3V6M
2 2
10U_0805_6.3V6M
2 2
10U_0805_6.3V6M
2
10U_0805_6.3V6M
AA5
VCC
VCC
VSS
VSS Y5
D12 VCCP VSS B19 AA7 VCC VSS Y21
D14 B22 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M AA9 Y24
VCCP VSS VCC VSS
D16 VCCP VSS B25 AA11 VCC VSS AA1
E11 C1 +CPU_CORE AA13 AA4
VCCP VSS VCC VSS
E13 VCCP VSS C4 AA15 VCC VSS AA6
E15 VCCP VSS C7 AA17 VCC VSS AA8
F10 VCCP VSS C10 1 1 1 1 1 1 1 AA19 VCC VSS AA10
F12 VCCP VSS C13 AA21 VCC VSS AA12
F14 C15 C265 C354 C307 C282 C332 C279 C298 AB6 AA14
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