Service Manuals, User Guides, Schematic Diagrams or docs for : acer Acer TravelMate 4220_4520_Wistron_Orta_RevSB
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5 4 3 2 1
Orta Block Diagram
PCB Layer Stackup
L1: Signal 1
L2: VCC
Project code: 91.4U101.001
DDR2 SODIMM L3: Inner Signal 2
PCB P/N : 48.4U101.0SA
D DIMM1
8,9
DDR II 533/667/800
AMD G792
36
REVISION : 06245-SB
L4: Inner Signal 3
L5: GND
D
DDR2 SODIMM K8 Rev.G L6: Signal 4
DDR II 533/667/800
DIMM2
8,9 S1g1 Socket 4,5,
6,7
CLK GEN. 14.318MHz
Power Switch ICS 9LPRS502 CPU V_CORE
HyperTransport
OUT
16x16
IN
P2231NFC1 28 (RTM875T-605) 3
INPUT OUTPUT
New card 28 PCI-E x 1 S-Vedio 13 DCBATOUT VCC_CORE_S0
Mini Card ATI CRT13
802.11a/b/g/n 28 PCI-E x 1 SYSTEM DC/DC
RJ45 TXFM LAN
10/100/1000 PCI-E x 1
RS690M LCD14 INPUT
DCBATOUT
OUTPUT
1D2V_S0
C C
24 24 1D8V_S3
BCM5787M 23
10,11,12,13
25MHz SYSTEM DC/DC
INT. MIC Array PCI-E x 4 INPUT OUTPUT
DCBATOUT 5V_S5
3D3V_S5
Line In
24.576MHz
30 Codec PCMCIA I/F SYSTEM LDO
AZALIA PCMCIA
30 ALC268 O2 SLOT INPUT OUTPUT
PWR SW
MIC In
29
ATI PCI BUS
OZ711 CP2211F
25
Support
TypeII
27
1D8V_S3 0D9V_S3
AMP SYSTEM LDO
1394 1394
B 30
G1432Q
30 SB600 25MHz
32.768KHz
Cardbus
Cardreader
CONN 27 MS/MS Pro/xD/
INPUT
3D3V_S5
OUTPUT
1D2V_S5
B
INT.SPKR MMC/SD/SDIO 3D3V_S0 2D5V_S0
6 in 1
25,26 27
AZALIA
3D3V_S0 1D5V_S0
AMP SYSTEM LDO
30 G1410Q LPC BUS
30 INPUT OUTPUT
Line Out
5V_AUX_S5
(No-SPDIF) DCBATOUT
MODEM USB SPI I/F BIOS LPC 3D3V_AUX_S5
16,17,18,19,20 KBC
Winbond W25X80-VSS
RJ11 MDC Card 32.768KHz 33 DEBUG
22 22 WPC8768L CONN. 33 Battery Charger
31
USB x 4
SATA INPUTS OUTPUTS
CCD .3M/1.3M
USB
USB
HDD 21 14 Touch INT. AD+ DCBATOUT
Pad 32 KB 32 BAT+
A
FIR 31 A
USB MINI USB
Wistron Incorporated
4 Port
22
BlueTooth
22 21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
CDROM PATA Finger print BLOCK DIAGRAM
Size Document Number Rev
21 22 A3
Orta SB
Date: Friday, January 12, 2007 Sheet 1 of 46
5 4 3 2 1
5 4 3 2 1
SA: 07/31/06 Start
D D
SB change
power team
1.change L7, L9 to 68.1R510.10D
2.changge U12 to 84.04706.037
3.change R66 to 10K ohm
C C
B B
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CHANGE HISTORY
Size Document Number Rev
A3 Orta SB
Date: Friday, January 12, 2007 Sheet 2 of 46
5 4 3 2 1
5 4 3 2 1
3D3V_S0 3D3V_CLK_VDD
1 R162 2
1
1
1
1
1
0R0603-PAD C279 3D3V_CLK_VDDA 3D3V_S0
C301 C302 C280 C282 C273 C306
2
2
2
2
2
2 R159 1
D
SB D
1
1
SC10U10V5ZY-1GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SC2D2U10V3ZY-1GP 0R0603-PAD
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SC2D2U10V3ZY-1GP C274 C281
SB
2
2
3D3V_S0
R181
1 2 3D3V_48MPWR_S0 SCD1U16V2ZY-2GP
SCD01U16V2KX-3GP
SC4D7U6D3V3KX-GP
1
1
C304 C305
2D2R3J-2-GP 3D3V_CLK_VDD
1- PLACE ALL SERIAL TERMINATION DY
RESISTORS CLOSE TO U800 SB
2
2
SC1U16V3ZY-GP U32
54 VDDCPU VDDA 50
2- PUT DECOUPLING CAPS CLOSE TO U800 3000mA.80ohm 14 49 R163 261R2F-GP
VDDSRC GNDA
POWER PIN 23 VDDSRC
28 56 CPUCLK_R R169 1 2 47D5R2F-1-GP
VDDSRC CPUCLK8T0 CPUCLK 6
44 55 CPUCLK#_R R170 1 2 47D5R2F-1-GP
VDDSRC CPUCLK8C0 CPUCLK# 6
5 VDD48 CPUCLK8T1 52
3D3V_S0 39 51
R182 2 0R0603-PAD VDDATIG CPUCLK8C1
1 2 VDDREF
60 16 1 4SRN33J-5-GP-U
VDDHTT SRCCLKT6 RN38 NBSRC_CLK 12
SRCCLKC6 17 2 3 NBSRC_CLK# 12
53 41 NBSRC_CLK_R
C303 GNDCPU ATIGCLKT0 NBSRC_CLK#_R
SB 15 GNDSRC ATIGCLKC0 40
SC2D2U10V3ZY-1GP 22 37
29
GNDSRC ATIGCLKT1
36
SB
GNDSRC ATIGCLKC1 SBLINK_CLK_R SRN33J-5-GP-U
C Parallel Resonance Crystal 45
8
GNDSRC ATIGCLKT2 35
34 SBLINK_CLK#_R
1
2 RN39
4
3
SBLINK_CLK 12
SBLINK_CLK# 12
C
C294 1 SC33P50V2JN-3GP GND48 ATIGCLKC2 SBSRC_CLK_R
2 38 GNDATIG ATIGCLKT3 30
1 31 SBSRC_CLK#_R 2 3 SRN33J-5-GP-U SBSRC_CLK 16
GNDREF ATIGCLKC3
1
1
X3 58 18 1 RN43 4
GNDHTT SRCCLKT5 SBSRC_CLK# 16
X-14D31818M-44GP
DY R172
1MR2J-L2-GP SRCCLKC5 19
CLK_PCIE_MINI_R
3 X1 SRCCLKT4 20 2 3 SRN33J-5-GP-U CLK_PCIE_MINI1 28
C283 21 CLK_PCIE_MINI#_R 1 RN41 4 CLK_PCIE_MINI1# 28
2
SRCCLKC4
1 2 4 24
2
X2 SRCCLKT3
SRCCLKC3 25 2 3 SRN33J-5-GP-U CLK_PCIE_NEW 28
26 CLK_PCIE_NEW_R 1 RN42 4
SC27P50V2JN-2-GP 3D3V_S0 R180 SRCCLKT2 CLK_PCIE_NEW# 28
27 CLK_PCIE_NEW#_R
3D3V_S0 SRCCLKC2 CLK_PCIE_LAN_R
1 2 11 RESET_IN# SRCCLKT0 47 1 4 SRN33J-5-GP-U CLK_PCIE_LAN 23
61 46 CLK_PCIE_LAN#_R 2 RN37 3
SB NC#61 SRCCLKC0
43
CLK_PCIE_LAN# 23
10KR2J-3-GP SRCCLKT1
1
SRCCLKC1 42
10KR2J-3-GPDY SRCCLKT7 12
13 DY 1 R168 2
R184 SRCCLKC7 10KR2J-3-GP TP33
9 57 CLK_REQA# 1 3D3V_CLK_VDD
9,19 SMBC0_SB
2
0R2J-2-GP 1 SMBCLK CLKREQA#
28 NEWCARD_CLKREQ# DY 2 R186 CLK_REQB#
9,19 SMBD0_SB 10 SMBDAT CLKREQB# 32 1 DY 2 R178 CLK_REQB# TPAD28
33 0R2J-2-GP
CLKREQC# R183 2
SB DY 1
48 7 10KR2J-3-GP TP40 TPAD30
IREF 48MHZ_1 CLK48_USB_R 1
Ioh = 5 * Iref DY 48MHZ_0 6 2 CLK48_USB 19
8
7
6
5
R171 33R2F-3-GP
(2.32mA) 475R2F-L1-GP R179 RN33
FS1/REF1 63 SB
Voh = 0.71V @ 60 ohm 1% 64 SRN10KJ-6-GP
FS0/REF0
FS2/REF2 62 06/05/2006
HTTCLK0 59
B B
06/09/2006
1
2
3
4
ICS951462YGLFT-GP
Check SLGO EXT CLK XSL84606 (56 Pin) or XSL84605 (64 Pin) pin to pin compatable with ICS951464
CLK_PCIE_NEW# 1 4
CLK_PCIE_NEW 2 RN45 3SRN49D9F-GP FS1 R165 2 1 33R2F-3-GP
FS0 SB_OSC_CLK 19
FS2 1 R166 2 33R2F-3-GP TP32TPAD30
EXT CLK FREQUENCY SELECT TABLE(MHZ) SBLINK_CLK# 2
DY 3
NB_OSC 12
SBLINK_CLK 1 RN36 4SRN49D9F-GP HTREF_CLK_R R1672 1
SB
33R2F-3-GP HTREF_CLK 12
FS2 FS1 FS0 CPU SRCCLK HTT PCI USB COMMENT
[2:1] DY
SBSRC_CLK# 1 4 CLK48_USB
SBSRC_CLK 2 RN46 3SRN49D9F-GP
1
0 0 0 Hi-Z 100.00 Hi-Z Hi-Z 48.00 Reserved
1
R161
NBSRC_CLK# DY 49D9R2F-GP EC61
0 0 1 X 100.00 X/3 X/6 48.00 Reserved 2 3
NBSRC_CLK 1 RN35 SRN49D9F-GP
SCD1U16V2ZY-2GP
4 DY
2
0 1 0 180.00 100.00 60.00 30.00 48.00 Reserved
2
CLK_PCIE_MINI1# DY
0 1 1 220.00 100.00 36.56 73.12 48.00 Reserved 1 4
CLK_PCIE_MINI1 2 RN44 3SRN49D9F-GP EMI REQUEST
1 0 0 100.00 100.00 66.66 33.33 48.00 Reserved
CLK_PCIE_LAN DY
1 0 1 133.33 100.00 66.66 33.33 48.00 Reserved 1 4
CLK_PCIE_LAN# 2 RN34 3SRN49D9F-GP
1 1 1 200.00 100.00 66.66 33.33 48.00 Normal ATHLON64 operation
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