Service Manuals, User Guides, Schematic Diagrams or docs for : acer Acer eMachines 350_Compal_LA-6311P_NAV51_Rev1.0
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A B C D E
1 1
Compal Confidential
2 2
NAV51 Schematics Document
Intel Pineview Processor with Tigerpoint + DDRII
3
2010-03-31 3
REV: 1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAV51 LA-6311P
Date: Tuesday, April 13, 2010 Sheet 1 of 33
A B C D E
A B C D E
Clock Generator Thermal Sensor
Compal Confidential CK505 page 8 EMC1402
page 5
Model Name : NAV51
CRT Conn
File Name : LA-6311P page 10
1 1
RGB
ZZZ Memory BUS(DDRII) DDRII-SO-DIMM
Pineview page 7
LCD Conn. LVDS FCBGA 559 1.8V DDRII 667
PCB
page 9 22x22mm
DA60000H810
page 4,5,6
DMI
X2 mode
GEN1
USB USB Port X2
2 PCI-Express Tigerpoint HDA page 20 2
PCBGA360 BlueTooth
page 15
17x17mm SATA
page 11,12,13,14
Azalia Codec CMOS CAM
MINI Card x1 10/100 Ethernet ALC272 page 9
AR8132L page 20
HDD
WLAN page 16
page 20 page 20
Card Reader
LPC BUS ENE UB6252
Transfermer
page 20
3 AMP & INT INT MIC HeadPhone & 3
MIC Jack
Speaker
RJ45 SD/MMC
Power ON/OFF DC/DC Interface CONN
page 25
page 18
3VALW/5VALW ENE KBC SPI
page 26 I/O Board
DC IN KB926
page 17
page 23
0.89VP/1.5VP
BATT IN 0.9VSP/2.5VSP
page 24 page 28
Int.KBD SPI ROM
page 19 page 17
CHARGER 1.8V/VCCP Touch Pad
page 25 page19
4
page 27 4
CPU_CORE
page 29
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAV51 LA-6311P
Date: Tuesday, April 13, 2010 Sheet 2 of 33
A B C D E
A B C D E
Voltage Rails
Power Plane Description S1 S3 S5 External PCI Devices
VIN Adapter power supply (19V) ON ON ON DEVICE IDSEL # REQ/GNT # PIRQ
B+ AC or battery power rail for power circuit. ON ON ON
1
+CPU_CORE Core voltage for CPU ON OFF OFF No PCI Device 1
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF
+VCCP VCCP switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+1.8V 1.8V power rail for DDR ON ON OFF
+0.89V Graphic core power rail ON OFF OFF
EC SM Bus1 address EC SM Bus2 address
+3VALW 3.3V always on power rail ON ON ON*
+3VS 3.3V switched power rail ON OFF OFF Device Address Device Address
+5VALW 5V always on power rail ON ON ON* Smart Battery 0001 011X b EMC1402 100_1100
+5VS 5V switched power rail ON OFF OFF
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. Tiger Point SM Bus address
SIGNAL Device Address
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
2 Clock Generator 2
1101 001Xb
Full ON HIGH HIGH HIGH ON ON ON ON (SLG8SP556VTR)
DDR DIMMA 1010 000Xb
S1(Power On Suspend) HIGH HIGH HIGH ON ON ON LOW
S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
USB table PCIE table
S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
Port0 MB USB Conn1.
S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF UHCI1 PCIE port1 LAN
Port1 MB USB Conn2.
Port2 PCIE port2 Wireless Card
EHCI1 UHCI2
Port3 CMOS
PCIE port3
Port4 Card Reader
BOARD ID Table(Page 17) UHCI3
Port5 PCIE port4
Vcc 3.3V +/- 5% Port6 BT
UHCI4 PCIE port5
Ra/Rc/Re 100K +/- 5% Port7 WLAN
Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max EHCI2 Port8 PCIE port6
UHCI5
0(EVT) 0 0 V 0 V 0 V Port9
3 3
1(DVT) 8.2K +/- 5% 0.216 V 0.250 V 0.289 V Port10
UHCI6
2(PVT) 18K +/- 5% 0.436 V 0.503 V 0.538 V Port11
3(MP) 33K +/- 5% 0.712 V 0.819 V 0.875 V
4 56K +/- 5% 1.036 V 1.185 V 1.264 V SATA table
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
SATA port0 HDD
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
7 NC 2.500 V 3.300 V 3.300 V SATA port1
SATA port2
BOARD ID Table
SATA port3
Board ID PCB Revision
SATA port4
0 0.1
1 0.2 SATA port5
2
3
4
4 4
5
6
7
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAV51 LA-6311P
Date: Tuesday, April 13, 2010 Sheet 3 of 33
A B C D E
5 4 3 2 1
(7) DDR_A_DQS#[0..7]
PINEVIEW_M
PINEVIEW_M (7) DDR_A_D[0..63]
U71A U71B
REV = 1.1
(7) DDR_A_DM[0..7]
REV = 1.1 DDR_A_MA0 AH19 AD3 DDR_A_DQS0
DMI_RX0_C (7) DDR_A_DQS[0..7] DDR_A_MA1 DDR_A_MA_0 DDR_A_DQS_0 DDR_A_DQS#0
F3 G2 DMI_TX0 (12) AJ18 AD2
DMI_RX#0_C DMI_RXP_0 DMI_TXP_0 DDR_A_MA2 DDR_A_MA_1 DDR_A_DQS#_0 DDR_A_DM0
F2 G1 DMI_TX#0 (12) AK18 AD4
DMI_RX1_C DMI_RXN_0 DMI_TXN_0 (7) DDR_A_MA[0..14] DDR_A_MA3 DDR_A_MA_2 DDR_A_DM_0
H4 DMI_RXP_1 DMI_TXP_1 H3 DMI_TX1 (12) AK16 DDR_A_MA_3
DMI_RX#1_C G3 J2 DMI_TX#1 (12) DDR_A_MA4 AJ14 AC4 DDR_A_D0
DMI_RXN_1 DMI_TXN_1 DDR_A_MA5 DDR_A_MA_4 DDR_A_DQ_0 DDR_A_D1
AH14 AC1
DMI
DDR_A_MA6 DDR_A_MA_5 DDR_A_DQ_1 DDR_A_D2
AK14 AF4
DDR_A_MA7 DDR_A_MA_6 DDR_A_DQ_2 DDR_A_D3
AJ12 DDR_A_MA_7 DDR_A_DQ_3 AG2
DDR_A_MA8 AH13 AB2 DDR_A_D4
D DDR_A_MA9 DDR_A_MA_8 DDR_A_DQ_4 DDR_A_D5 D
AK12 AB3
DDR_A_MA10 DDR_A_MA_9 DDR_A_DQ_5 DDR_A_D6
(8) CLK_CPU_EXP# N7 EXP_CLKINN EXP_RCOMPO L10 AK20 DDR_A_MA_10 DDR_A_DQ_6 AE2
N6 L9 R162 DDR_A_MA11 AH12 AE3 DDR_A_D7
(8) CLK_CPU_EXP EXP_CLKINP EXP_ICOMPI DDR_A_MA_11 DDR_A_DQ_7
L8 R203 49.9_0402_1% DDR_A_MA12 AJ11
EXP_RBIAS 750_0402_1% DDR_A_MA13 DDR_A_MA_12 DDR_A_DQS1
R10 AJ24 AB8
EXP_TCLKINN DDR_A_MA14 DDR_A_MA_13 DDR_A_DQS_1 DDR_A_DQS#1
R9 N11 T38 AJ10 AD7
EXP_TCLKINP RSVD_TP DDR_A_MA_14 DDR_A_DQS#_1 DDR_A_DM1
N10 RSVD RSVD_TP P11 T39 Must be placed within 500 mils from Pineview-M pins DDR_A_DM_1 AA9
N9 RSVD DDR_A_WE# AK22 AB6 DDR_A_D8
(7) DDR_A_WE# DDR_A_WE# DDR_A_DQ_8
DDR_A_CAS# AJ22 AB7 DDR_A_D9
(7) DDR_A_CAS# DDR_A_CAS# DDR_A_DQ_9
DDR_A_RAS# AK21 AE5 DDR_A_D10
(7) DDR_A_RAS# DDR_A_RAS# DDR_A_DQ_10 DDR_A_D11
K2 RSVD RSVD K3 DDR_A_DQ_11 AG5
J1 L2 DDR_A_BS0 AJ20 AA5 DDR_A_D12
RSVD RSVD (7) DDR_A_BS0 DDR_A_BS1 DDR_A_BS_0 DDR_A_DQ_12 DDR_A_D13
M4 RSVD RSVD M2 (7) DDR_A_BS1 AH20 DDR_A_BS_1 DDR_A_DQ_13 AB5
L3 N2 DDR_A_BS2 AK11 AB9 DDR_A_D14
RSVD RSVD (7) DDR_A_BS2 DDR_A_BS_2 DDR_A_DQ_14
AD6 DDR_A_D15
DDR_A_DQ_15
1 OF 6 DDR_A_DQS2
PINEVIEW-M_FCBGA8559 DDR_A_DQS_2 AD8
DDR_CS#0 AH22 AD10 DDR_A_DQS#2
(7) DDR_CS#0 DDR_CS#1 DDR_A_CS#_0 DDR_A_DQS#_2 DDR_A_DM2
(7) DDR_CS#1 AK25 DDR_A_CS#_1 DDR_A_DM_2 AE8
JP16 AJ21
XDP_PREQ# CONN@ DDR_A_CS#_2 DDR_A_D16
(5) XDP_PREQ# 1 1 AJ25 DDR_A_CS#_3 DDR_A_DQ_16 AG8
(5) XDP_PRDY# XDP_PRDY# 2 AG7 DDR_A_D17
2 DDR_CKE0 DDR_A_DQ_17 DDR_A_D18
3 (7) DDR_CKE0 AH10 AF10
XDP_BPM#3 3 DDR_CKE1 DDR_A_CKE_0 DDR_A_DQ_18 DDR_A_D19
(5) XDP_BPM#3 4 4 (7) DDR_CKE1 AH9 DDR_A_CKE_1 DDR_A_DQ_19 AG11
(5) XDP_BPM#2 XDP_BPM#2 5 AK10 AF7 DDR_A_D20
5 DDR_A_CKE_2 DDR_A_DQ_20 DDR_A_D21
6 6 AJ8 DDR_A_CKE_3 DDR_A_DQ_21 AF8
C435 DMI_RX0_C XDP_BPM#1 7 AD11 DDR_A_D22
(12) DMI_RX0 1 2 (5) XDP_BPM#1 7 DDR_A_DQ_22
0.1U_0402_10V7K (5) XDP_BPM#0 XDP_BPM#0 8 M_ODT0 AK24 AE10 DDR_A_D23
8 (7) M_ODT0 M_ODT1 DDR_A_ODT_0 DDR_A_DQ_23
9 (7) M_ODT1 AH26
C436 R354 1 9 DDR_A_ODT_1 DDR_A_DQS3
(12) DMI_RX#0 1 2 DMI_RX#0_C (5,13) H_PWRGD 2 1K_0402_5% 10 10 AH24 DDR_A_ODT_2 DDR_A_DQS_3 AK5
R347 1 2 1K_0402_5% 11 AK27 AK3 DDR_A_DQS#3
C 0.1U_0402_10V7K (13) SLPIOVR# 11 DDR_A_ODT_3 DDR_A_DQS#_3 C
12 AJ3 DDR_A_DM3
C437 (8) CPU_ITP 12 DDR_A_DM_3
1 2 DMI_RX1_C (8) CPU_ITP# 13
(12) DMI_RX1 13 DDR_A_D24
0.1U_0402_10V7K +VCCP 14 AH1
PLTRST# 1 R348 14 M_CLK_DDR0 DDR_A_DQ_24 DDR_A_D25
C438 (5,13,16,17,21) PLTRST# 2 1K_0402_1% 15 15 (7) M_CLK_DDR0 AG15 DDR_A_CK_0 DDR_A_DQ_25 AJ2
(12) DMI_RX#1 1 2 DMI_RX#1_C 16 M_CLK_DDR#0 AF15 AK6 DDR_A_D26
16 (7) M_CLK_DDR#0 M_CLK_DDR1 DDR_A_CK_0# DDR_A_DQ_26 DDR_A_D27
0.1U_0402_10V7K 17 17 (7) M_CLK_DDR1 AD13 DDR_A_CK_1 DDR_A_DQ_27 AJ7
(5) XDP_TDO XDP_TDO 18 ◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo