Service Manuals, User Guides, Schematic Diagrams or docs for : acer Acer eMachines D640_Wistron_JV42-DN_Rev-2
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5 4 3 2 1
Project code: 91.4HD01.001
JV42-DN Block Diagram PCB P/N : 48.4GX01.0SA
PCB
REVISION
: 09919 SA
: PCB STACKUP SYSTEM
DDR3 800/1066/1333MHz CRT
TOP
DC/DC
D
AMD Champlain CPU 20 RT8223 46 D
16,17 S1G4 (45W) INPUTS OUTPUTS
VCC
LCD DCBATOUT
5V_S5(5.5A)
19
DDR3 638-Pin uFCPGA638
4,5,6,7
S 3D3V_S5(5A)
800/1066/1333 MHz 800/1066/1333MHz HDMI S SYSTEM DC/DC
16,17 21 GND RT8209E 47
5V_S5 1D5V_S3(14A)
OUT
HT 3.0 BOTTOM RT9026 47
IN
16X16 0D75_S3(1.2A)
5V_S5
Madison
DDR3 SYSTEM DC/DC
CLK GEN. 3 North Bridge ATI VRAM RT8209E 48
16X
AMD RS880M 53,54,55,56,57 58, 59, 60, 61 INPUTS
ICS9LPRS480BKLFT 71.09480.A03
CPU I/F LVDS, CRT I/F PCI EXPRESS GRAPHIC
RTM880N-796-VB-GRT 71.00880.A03 DCBATOUT 1D1V_S0(11A)
INTEGRATED GRAHPICS LAN
Giga LAN TXFM RJ45 RT9025 48
27 27
C
BCM57780 26 3D3V_S5 1D1V_S5(1.4A) C
INT MIC 8,9,10
RT9025 49
30
5V_S5 1D1V_VGA
A-Link PCIex1
Codec AZALIA 4X1 Mini Card RT9161 49
ALC272 WLAN 33
3D3V_S0 2D5V_S0
28 (200mA)
MIC In South Bridge RT9025 49
30 AMD SB820
LPC BUS
1D5V_S3 1D05V_S0
(1.4A)
INT.SPKR USB 2.0/1.1 ports
ETHERNET (10/100/1000Mb)
BIOS CHARGER
30 OP AMP High Definition Audio KBC MXIC
MX25L1605
LPC BQ24745 50
29 ATA 66/100
Novoton 37 DEBUG INPUTS OUTPUTS
NPCE781B CONN.37
B Line Out 36
CHG_PWR
B
ACPI 1.1
18V 6.0A
LPC I/F DCBATOUT
UP+5V
30
PCI/PCI BRIDGE
Touch INT. 5V 100mA
11,12,13,14,15 Pad 38 KB 36
CPU DC/DC
ISL6265AHR 45
SATA USB INPUTS OUTPUTS
CardReader
MS/MS Pro/xD
AU6433 VCC_CORE_S0
/MMC/SD
32 5 in 1 32 0~1.55V 18A
DCBATOUT
HDD SATA Mini USB
22 Blue Tooth 24 VDDNB
USB 0~1.55V 4A
3 Port 25
ODD SATA
A 23 Diserete Madison Hynix A
Camera Daughter Board Daughter Board
USB Board PWR+LED Board Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
BLOCK DIAGRAM
Size Document Number Rev
A3
JE40-DN -2
Date: Monday, March 08, 2010 Sheet 1 of 63
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A Diserete Madison Hynix A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
History
Size Document Number Rev
A3
JE40-DN -2
Date: Monday, March 08, 2010 Sheet 2 of 63
5 4 3 2 1
5 4 3 2 1
3D3V_S0 3D3V_CLK_VDD
3D3V_S0
1 R425 2 R177
Do Not Stuff 1 2 3D3V_48MPWR_S0
1
1
1
1
1
1
1
1
1
C677 C678 DY C713 C689 C680 C360 C724 C707 C727 Due to PLL issue on current clock chip, the SBlink clock
1
1
Do Not Stuff
SC10U10V5ZY-1GP
Do Not Stuff
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
Do Not Stuff
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY DY 2R3J-GP C358 C359
SC1U10V2KX-1GP need to come from SRC clocks for RS740 and RS780.
DY
2
2
2
2
2
2
2
2
2
Do Not Stuff
Future clock chip revision will fix this.
-1 0203
2
2
3000mA.80ohm
D D
Clock chip has internal serial terminations
3D3V_S0 for differencial pairs, external resistors are
reserved for debug purpose.
1 R433 2
Do Not Stuff
1D1V_CLK_VDDIO
1202
C733
SC12P50V2JN-L1-GP
1 2
1
1
1
1
1
1
1
C690 C691 C702 C712 C681 C682 C726 3D3V_CLK_VDD 2ND = 82.30005.901
1
Do Not Stuff
SC10U6D3V3MX-GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY 82.30005.A51
U51 X6
2
2
2
2
2
2
2
1D1V_CLK_VDDIO X-14D31818M-50GP
GEN_XTAL_IN C734
26 61
2
VDDATIG X1 GEN_XTAL_OUT SC12P50V2JN-L1-GP
25 62 1 2
VDDATIG_IO X2
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