Service Manuals, User Guides, Schematic Diagrams or docs for : acer Acer eMachines G520_G720_Quanta_ZY6D_Rev2B
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5 4 3 2 1
ZY6D SYSTEM BLOCK DIAGRAM
BOM MARK X'TAL
14.318MHZ
CPU
E@ EXT VGA
Penryn 479
D
268@ AUDIO 268 CLOCK GENERATOR uFCPGA P3,P4 Thermal Sensor P3 D
D@ DOCK ICS: ICS9LPRS365BGLFT
D2@ DDR2 SELGO: SLG8SP512K05
SP@ (EXT VGA OR DDR2) P2
ED2@ EXT VGA & DDR2
CB@ CARDBUS FSB 667/800/1067 Mhz
NSF@ Non ASF
DDRII
I@ INT VGA
888@ AUDIO 888
SO-DIMM 0 Dual Channel DDR2
D3@ DDR3 SO-DIMM 1 667/800 MHz NB
P16 CRT
ND@ NON DOCK
Cantiga Page:19
ID2@ INT VGA & DDR2
ED3@ EXT VGA & DDR3 PM965 LVDS
ID3@ INT VGA & DDR3
Page:19
C ASF@ ASF P5,P6,P7,P8,P9,P10,P11 C
NCB@ NON CARDBUS
X4 DMI interface
HDD (SATA)*2
LOW COST
1. MINI CARD 1 SLOT P25
2. NON DOCK
3. NON CARDBUS
4. NON ASF
5. NON HDMI SATA0 PCI-Express
SATA1
ODD (SATA)
SATA4 SB
P25 PCIE-4
WLAN
ICH9M
USB 2.0 PCIE-6
P23
B
P12,P13,P14,P15 B
X'TAL X'TAL
Azalia 32.768KHZ 25M
USB Port x 4
USB0~3 P25 BROADCOM
Int MIC 10/100/1G LAN
P27 LPC
CCD 5764M P21
USB7 P19
EC (WPC8769LDG)
Azalia Audio SWITCH CIRCUIT
P32 Page:22 LAN
Audio Amplifier Controller X'TAL Page: 33
32.768K
P27 & 28 P27
ALC268 & 888
Transformer
P22
SPI ROM
P32
A RJ45 A
Touch Pad P22
Connector
P32
Quanta Computer Inc.
K/B COON. PROJECT : ZY6D
Speaker Phone Jack SPDIF Line in MIC Jack Fan Header
P28 P28 P28 P28 P28 P32 P31 Size Document Number Rev
Block Diagram 1A
Date: Thursday, August 28, 2008 Sheet 1 of 40
5 4 3 2 1
5 4 3 2 1
Clock Generator
U25 CLK VDD power range 1.05V~3.3V
+3V R255 BKP1608HS181-T +3V_CLK 2 12 +1V05_CLK BKP1608HS181-T R219 +1.05V
VDD_PCI VDD_I/O
9 VDD_48 VDD_PLL3_I/O 20
16 26 C272 C213 C265 C214 C212 C261 C267
C216 C219 C215 C257 C262 C260 C263 VDD_PLL3 VDD_SRC_I/O_1
39 VDD_SRC VDD_SRC_I/O_2 36
55 45 10U/6.3V_8 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4
.1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 *10U/6.3V_8 VDD_CPU VDD_SRC_I/O_3
D 61 VDD_REF VDD_CPU_I/O 49 D
CPU_STOP# 37 PM_STPCPU# <14>
PCI_STOP# 38 PM_STPPCI# <14>
56 Pin 56 : It acts as a
CKPWRGD/PD# CK_PWRGD <14>
level sensitive strobe
R254 Change from 33 to 475 CG_XOUT 59 54 CLK_CPU_BCLK_R RP13 1 2 0X2_4 to latch the FS pins
XTAL_OUT CPU_0 CLK_CPU_BCLK <3> and other multiplexed
CG_XIN 60 53 CLK_CPU_BCLK#_R 3 4
XTAL_IN CPU_0# CLK_CPU_BCLK# <3> inputs.
<14> SATACLKREQ# R246 475/F_4 SATACLKREQ#_R 1 51 CLK_MCH_BCLK_R RP12 1 2 0X2_4
PCI_0/CLKREQ_A# CPU_1_MCH CLK_MCH_BCLK <5>
R254 *475/F_4 NEW_CLKREQ#_R 3 50 CLK_MCH_BCLK#_R 3 4
<29> NEW_CLKREQ# PCI_1/CLKREQ_B# CPU_1_MCH# CLK_MCH_BCLK# <5>
R253 33_4 PCLK_MINI_R 4 47 CLK_PCIE_CARD_R RP11 1 2 *0X2_4
<23> PCLK_DEBUG PCI_2 SRC_8/CPU_ITP CLK_PCIE_CARD <28>
R252 33_4 PCLK_591_R 5 46 CLK_PCIE_CARD#_R 3 4
<32> PCLK_591 PCI_3 SRC_8#/CPU_ITP# CLK_PCIE_CARD# <28>
R264 *33_4 PCLK_PCM_R 6
<27> PCLK_PCM ^PCI_4/LCDCLK_SEL
PCLK_ICH R263 33_4 PCLK_ICH_R 7
<13> PCLK_ICH PCIF_5/ITP_EN
NC 48
CPU_BSEL0 R258 2.2K_4
R261 33_4 FSA 10
<14> CLKUSB_48 MCH_BSEL1 USB_48MHz/FS_A
57 FS_B/TEST_MODE
17 CLK_DREFSSCLK_R RP15 3 4 I@0X2
LCDCLK/27M CLK_DREFSSCLK <6>
CPU_BSEL2 R230 10K_4 18 CLK_DREFSSCLK#_R 1 2
LCDCLK#/27M_SS CLK_DREFSSCLK# <6>
R229 33_4 FSC 62
<14> 14M_ICH REF/FS_C/TEST_SEL
*30P/50V_4 C209
RP16 4 3 I@0X2 DREFCLK_R 13 21 CLK_PCIE_SATA_R RP18 3 4 0X2_4
<6> CLK_DREFCLK SRC_0/DOT_96 SRC_2 CLK_PCIE_SATA <12>
2 1 DREFCLK#_R 14 22 CLK_PCIE_SATA#_R 1 2
<6> CLK_DREFCLK# SRC_0#/DOT_96# SRC_2# CLK_PCIE_SATA# <12>
24 CLK_PCIE_LAN_R RP17 3 4 0X2_4
SRC_3/CLKREQ_C# CLK_PCIE_LAN <21>
CGCLK_SMB 64 25 CLK_PCIE_LAN#_R 1 2
C SCL SRC_3#/CLKREQ_D# CLK_PCIE_LAN# <21> C
CGDAT_SMB 63 27 CLK_PCIE_NEW_C_R RP20 3 4 *0X2_4
SDA SRC_4 CLK_PCIE_NEW_C <29>
28 CLK_PCIE_NEW_C#_R 1 2
SRC_4# CLK_PCIE_NEW_C# <29>
41 CLK_PCIE_ICH_R RP9 1 2 0X2_4
SRC_6 CLK_PCIE_ICH <13>
40 CLK_PCIE_ICH#_R 3 4
SRC_6# CLK_PCIE_ICH# <13>
44 PECLK_VGA_R RP10 1 2 *E@0X2 Rev:B Swap SRC9 & SRC4
SRC_7/CLKREQ_F# CLK_MXM <18>
8 43 PECLK_VGA#_R 3 4
VSS_PCI SRC_7#/CLKREQ_E# CLK_MXM# <18>
11 30 CLK_PCIE_MINI1_R RP19 3 4 *0X2_4
VSS_48 SRC_9 CLK_PCIE_MINI1 <23>
15 31 CLK_PCIE_MINI1#_R 1 2
VSS_I/O SRC_9# CLK_PCIE_MINI1# <23>
19 34 CLK_PCIE_3GPLL_R RP8 3 4 0X2_4
VSS_PLL3 SRC_10 CLK_PCIE_3GPLL <6>
23 35 CLK_PCIE_3GPLL#_R 1 2
VSS_SRC_1 SRC_10# CLK_PCIE_3GPLL# <6>
29 33 CLK_PCIE_TV_R RP14 1 2 0X2_4
VSS_SRC_2 SRC_11/CLKREQ_H# CLK_PCIE_TV <23>
42 32 CLK_PCIE_TV#_R 3 4
VSS_SRC_3 SRC_11#/CLKREQ_G# CLK_PCIE_TV# <23>
+3V 52 VSS_CPU
Clock Gen I2C
58 VSS_REF
Q26 R237 R243 SLG8SP512 Rev:C Change C 205 & C204 P/N to CH03306JB04 +3V
RHU002N06
2
10K_4 10K_4 SATACLKREQ#_R R475 10K_4
C205 33P/50V_4 CG_XIN
3 1 CGDAT_SMB NEW_CLKREQ#_R R531 *10K_4
<14,16,20,21,23,29> PDAT_SMB
QCI P/N Y8 PCLK_MINI_R R532 10K_4
14.318MHz
+3V
B SLG8SP512 AL8SP512K05 C204 33P/50V_4 CG_XOUT Rev:B for vendor request B
Q27
RHU002N06
2
ICS9LPRS365BGLFT ALPRS365K13
Strap table
3 1 CGCLK_SMB
<14,16,20,21,23,29> PCLK_SMB
PCLK_PCM_R R260 10K_4
CPU Clock select BSEL Frequency Select Table
FSC FSB FSA Frequency Pin 6 : For Pin 13/14 and 17/18 selection
0 = LCDCLK & DOT96 for internal graphic controller support
1 = 27M & 27M_SS &SRC_0 for external graphic controller support
Pin 10/57/62 : For Pin CPU frequency selection 0 0 0 266Mhz
0 0 1 133Mhz PCLK_ICH_R R259 10K_4
R262 0_4
<3> CPU_BSEL0 MCH_BSEL0 <6>
0 1 1 166Mhz
Pin 7 : For Pin 46/47 selection
1 = CPU_ITP
0 = SRC_8
A 0 1 0 200Mhz A
R226 0_4
<3> CPU_BSEL1 MCH_BSEL1 <6>
1 1 0 400Mhz
Quanta Computer Inc.
CRB Rev0.7 : 110(CBA) 1 1 1 Reserved
PROJECT : ZY2 & ZY6
R231 0_4 1 0 1 100Mhz
<3> CPU_BSEL2 MCH_BSEL2 <6>
Size Document Number Rev
CLOCK GENERATOR CK505 W/REGULATOR 1A
1 0 0 333Mhz
Date: Thursday, August 28, 2008 Sheet 2 of 40
5 4 3 2 1
5 4 3 2 1
<5> H_A#[3..16]
U40A
H_A#3 J4 H1 U40B
A[3]# ADS# H_ADS# <5>
ADDR GROUP_0
H_A#4 L5 E2 H_D#[0..15] H_D#[32..47]
H_A#5 A[4]# BNR# H_BNR# <5> <5> H_D#[0..15] H_D#0 H_D#32 H_D#[32..47] <5>
L4 A[5]# BPRI# G5 H_BPRI# <5> E22 D[0]# D[32]# Y22
H_A#6 K5 H_D#1 F24 AB24 H_D#33
H_A#7 A[6]# H_D#2 D[1]# D[33]# H_D#34
M3 A[7]# DEFER# H5 H_DEFER# <5> E26 D[2]# D[34]# V24
DATA GRP 0
DATA GRP 0
H_A#8 N2 F21 H_D#3 G22 V26 H_D#35
A[8]# DRDY# H_DRDY# <5> D[3]# D[35]#
DATA GRP 2
H_A#9 J1 E1 H_D#4 F23 V23 H_D#36
A[9]# DBSY# H_DBSY# <5> +1.05V D[4]# D[36]#
H_A#10 N3 H_D#5 G25 T22 H_D#37
H_A#11 A[10]# H_D#6 D[5]# D[37]# H_D#38
P5 A[11]# BR0# F1 H_BREQ# <5> E25 D[6]# D[38]# U25
H_A#12 P2 H_D#7 E23 U23 H_D#39
D A[12]# D[7]# D[39]# D
CONTROL
H_A#13 L2 D20 H_IERR# R162 56.2/F_4 H_D#8 K24 Y25 H_D#40
H_A#14 A[13]# IERR# H_D#9 D[8]# D[40]# H_D#41
P4 A[14]# INIT# B3 H_INIT# <12> G24 D[9]# D[41]# W22
H_A#15 P1 H_D#10 J24 Y23 H_D#42
A[15]# H_LOCK# <5> D[10]# D[42]#
H_A#16 R1 H4 H_D#11 J23 W24 H_D#43
A[16]# LOCK# T16 D[11]# D[43]#
M1 H_D#12 H22 W25 H_D#44
<5> H_ADSTB#0 ADSTB[0]# H_CPURST# <5> D[12]# D[44]#
C1 H_D#13 F26 AA23 H_D#45
<5> H_REQ#[0..4] RESET# H_RS#[0..2] <5> D[13]# D[45]#
H_REQ#0 K3 F3 H_RS#0 H_D#14 K22 AA24 H_D#46
H_REQ#1 REQ[0]# RS[0]# H_RS#1 H_D#15 D[14]# D[46]# H_D#47
H2 REQ[1]# RS[1]# F4 H23 D[15]# D[47]# AB25
H_REQ#2 K2 G3 H_RS#2 J26 Y26
REQ[2]# RS[2]# <5> H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 <5>
H_REQ#3 J3 G2 H26 AA26
H_REQ#4 REQ[3]# TRDY# H_TRDY# <5> <5> H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 <5>
L1 REQ[4]# <5> H_DINV#0 H25 DINV[0]# DINV[2]# U22 H_DINV#2 <5>
<5> H_A#[17..35] HIT# G6 H_HIT# <5>
H_A#17 Y2 E4 H_D#[16..31] H_D#[48..63]
A[17]# HITM# H_HITM# <5> <5> H_D#[16..31] H_D#[48..63] <5>
H_A#18 U5 H_D#16 N22 AE24 H_D#48
H_A#19 A[18]# XDP_BPM#0 H_D#17 D[16]# D[48]# H_D#49
R3 A[19]# BPM[0]# AD4 T10 K25 D[17]# D[49]# AD24
ADDR GROUP_1
ADDR GROUP_1
H_A#20 W6 AD3 XDP_BPM#1 H_D#18 P26 AA21 H_D#50
A[20]# BPM[1]# T15 D[18]# D[50]#
H_A#21 U4 AD1 XDP_BPM#2 H_D#19 R23 AB22 H_D#51
A[21]# BPM[2]# T13 D[19]# D[51]#
H_A#22 Y5 AC4 XDP_BPM#3 H_D#20 L23 AB21 H_D#52
A[22]# BPM[3]# T11 D[20]# D[52]#
XDP/ITP SIGNALS
DATA GRP 1
H_A#23 U1 AC2 XDP_BPM#4 T14 H_D#21 M24 AC26 H_D#53
DATA GRP 3
H_A#24 A[23]# PRDY# XDP_BPM#5 H_D#22 D[21]# D[53]# H_D#54
R4 A[24]# PREQ# AC1 L22 D[22]# D[54]# AD20
H_A#25 T5 AC5 XDP_TCK H_D#23 M23 AE22 H_D#55
H_A#26 A[25]# TCK XDP_TDI Connect it to CPU DBR# is for ITP debug port H_D#24 D[23]# D[55]# H_D#56
T3 A[26]# TDI AA6 P25 D[24]# D[56]# AF23
H_A#27 W2 AB3 XDP_TDO or CPU interposer (like ICE) to reset the system H_D#25 P23 AC25 H_D#57
H_A#28 A[27]# TDO XDP_TMS H_D#26 D[25]# D[57]# H_D#58
W5 A[28]# ◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo