Service Manuals, User Guides, Schematic Diagrams or docs for : acer Acer_Aspire_3040_-_5040_-_Bolsena-EAB2
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5 4 3 2 1
See 'TEXT' in 0MEMO or 1MEMO property in component
Dummy when use '10/100'
Dummy when use 'GIGA'
Bolsena-E(AB2) Block Diagram Project Code: 91.4G401.001
REVISION: 05236-SA
200-PIN DDR SODIMM
Dummy when use 'UMA' CLK GEN
Dummy when use 'DIS'
AMD CPU DDR 333/400
IDT CV1373 DDR x2
D 35W/25W PCB Layer Stackup D
Dummy when use 'SATA' 8,9,10
L1: Signal 1
Dummy when use 'IDE' LEDs 16
4,5,6,7 L2:VCC
RTC BAT. 17
BUTTONs 33 L3: Signal 2
PWR SW L4: Signal 3
HyperTransport
CP2211 tv
PCMCIA 26
ENE 6.4GB/S 16b/8b 16 L5: GND
SLOT CB1410 L6: Signal 4
PCMCIA I/F
Support LVDS
TypeII
1* Slot Cardbus ATI LCD 16
26 Power Block Diag -> Page 40
RS482M
AGTL+ CPU I/F + UMA
25 PCI Express x16 ATI
11,12,13,14 RGB CRT
M52P CRT 15
MS/MS Pro/xD/ 49,50,51,52,53
C
MMC/SD 5 in 1 28
RICOH PCI-Express C
R5C832 x2 VRAM x4
1394 1394 54,55
28 CardReader
CONN 27,28
ATI BlueTooth
SB450 miniUSB
Mini-PCI PCI Bus / 33MHz 23
ACPI 2.0 6xUSB 2.0
USB x 4
802.11a/b/g PCI 24
29 CODEC Line In 3
AZALIA ALC883 MIC In
32
AZALIA
RJ45 TXFM 1000Mb PCI LAN Line Out33
31 31
MODEM RJ11
Realtek OP AMP
MDC Card CONN
RTL8110SBL 31 G1421
23 33
1000/100/10 Int. SPKR33
TXFM 10/100Mb
B
RTL8100C B
31 100/10 30 LPC Bus / 33MHz
LPC I/F
ATA 133 17,18,19,20,21
NS SIO
Thermal
PIDE
SIDE
PC87381 KBC XBUS
& Fan
37 KB3910
DVD/ G792 23 34
SATA HDD
CD-RW
24 24 24
Touch Int.
FIR ISA ROM
Pad KB
TFDU6102 35 35 36
37
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
BLOCK DIAGRAM
Size Document Number Rev
A3 SA
Bolsena-E
Date: Thursday, October 13, 2005 Sheet 1 of 58
5 4 3 2 1
5 4 3 2 1
PCI Routing
IDSEL IRQ REQ/GNT
MiniPCI 21 F 0
LAN 23 H 2
D D
7411 22 E (CardBus) 1
7411 17 G (1394) 3
7411 17 E (FlashMedia) 3
C C
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B B
Ref. function schematic BOM
-------------------------
U81 cpu socket 62.10055.121 (DON'T CHANGE) (3mm high)
U80 north bridge 71.RS482.M03 71.RS482.M03 (ver A12)
U43 south bridge 71.SB400.B0U 71.SB400.D0U (ver A13)
U32 clock gen. 71.00137.C0W 71.00137.C0W
---
U70 VGA M52 71.0M52P.A0U
U64 VRAM FOR M52
U65 VRAM FOR M52
U69 VRAM FOR M52
U71 VRAM FOR M52
---
U66 BIOS SOCKET 72.39040.G03 62.10002.032 (NO NEED WHEN PD)
A U66 BIOS IC 72.39040.G03 72.39040.H03 (DIP STAGE IN LAB, SMT IN PD) A
---
U75 GIGA LAN 71.08110.00G 71.08110.A0G
U75 10/100 LAN 71.08110.00G 71.08100.C0G
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
HISTORY
Size Document Number Rev
A3 SA
Bolsena-E
Date: Thursday, October 13, 2005 Sheet 2 of 58
5 4 3 2 1
A B C D E
3D3V_S0
3D3V_S0 3D3V_CLK_VDD 3D3V_CLK_VDDA
1 L13 2 1 L15 2
0R0603-PAD 0R0603-PAD
1
1
1
1
1
1
1
C490 C476 C443 C445 C444 C487 C496
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SC10U10V5ZY-1GP SCD1U16V2ZY-2GP SC10U10V5ZY-1GP
2
2
2
2
2
2
2
RN53
2 3 SRN33J-5-GP-U SBLINK_CLK# 13
3D3V_CLK_VDDA 1 4 SBLINK_CLK 13
1
1
1
1
4 1 4 RN47 SBSRC_CLK# 17 4
C485 C486 C489 C488 3D3V_S0 3D3V_CLK_VDD 2 3 SBSRC_CLK 17
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP U23 SRN33J-5-GP-U
2
2
2
2
1 L14 2 3D3VDD48_S0 3 33 SRC_CLK0#
0R0603-PAD VDD_48 SRCC0 SRC_CLK0
39 VDDA SRCT0 34
1
32 25 SRC_CLK3#
C446 VDD_SRC SRCC3 SRC_CLK3
SRCT3 24
SC2D2U16V5ZY-GP 21 23
2
VDD_SRC SRCC4
14 VDD_SRC SRCT4 22
35 VDD_SRC SRCC5 19
SRCT5 18
56 VDD_REF SRCC6 17
51 VDD_PC1 SRCT6 16
1 2 C459 XI_CLK 43 13
SC33P50V2JN-3GP VDD_CPU SRCC7
48 VDD_HTT SRCT7 12
1
2
R223 40
X2 DUMMY-R3 CPUC1
1 XIN CPUT1 41
X-14D318MHZ-18GP 2 44 CPUCLKJ_CY 1 R247 2 15R2J-L1-GP CPUCLK# 6
XOUT CPUC0 CPUCLK_CY R248 2 15R2J-L1-GP
45 1 CPUCLK 6
1
USB_48M CPUT0
4
2
XO_CLK SMBC_CLK USB_48
1 2 C472 7 SCL
RN52
SC33P50V2JN-3GP SMBD_CLK 8 29 ATI_CLK0# 2 3 NBSRC_CLK# 13
SDA SRCC1 ATI_CLK0
SRCT1 30 1 4 NBSRC_CLK 13
1 R218 2 22R2J-2-GP 10 28 ATI_CLK1#
20 CLK48_USB CLKREQ0# SRCC2 ATI_CLK1
11 27 SRN33J-5-GP-U
CLKREQ1# SRCT2
8,20 SMBD_SB 2 3
1 4 RN46
3 8,20 SMBC_SB RN48 SRN33J-5-GP-U FS2 3
9 SEL24/24_48# VSS_SRC 36 1 4 GFX_CLK# 49
2 3 FS1 53 20 2 3 GFX_CLK 49
13 CLK14_NB FS0 REF1 VSS_SRC
20 SB_OSC_CLK 1 4 54 REF0 RESET# 15
RN54 SRN33J-5-GP-U 26 SRN33J-5-GP-U
R242 2 33R2J-2-GP TURBO1
1 52
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37 CLK14_SIO REF2
13 HTREF_CLK CLK_HTT66 47 VSS_CPU 42 Dummy when use UMA
1 2 HTT66 VSS_PCI 49
R241 75R2F-2-GP 50 46 RN58 SRN49D9F-GP
PCI0 VSS_HTT SBLINK_CLK
VSS_SRC 31 2 3
IREF_CLKGEN 37 38 SBLINK_CLK# 1 4
IREF VSSA
1 VSS_48 5
1
6 NC#6 VSS_REF 55
R249 R240 RN38 SRN49D9F-GP
100R2F-L1-GP-U 475R2F-L1-GP SBSRC_CLK# 2 3
IDTCV137PAG-2-GP SBSRC_CLK 1 4
71.00137.C0W
2
2
RN37 SRN49D9F-GP
GFX_CLK# 1 4
GFX_CLK 2 3
Dummy when use UMA
2 2
RN57 SRN49D9F-GP
NBSRC_CLK# 2 3
NBSRC_CLK 1 4
3D3V_CLK_VDD
DY
1 R245 2 FS0
2K2R2J-2-GP
1 2
DUMMY-R2
R246
1 R243 2 DY FS1
2K2R2J-2-GP
1 2
DUMMY-R2
R244
1 1
1 R216 2 DY FS2
2K2R2J-2-GP
1 2 Wistron Corporation
DUMMY-R2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
R217 Taipei Hsien 221, Taiwan, R.O.C.
for ICS
Title
CLKGEN_IDTCV137
Size Document Number Rev
A3 SA
Bolsena-E
Date: Thursday, October 13, 2005 Sheet 3 of 58
A B C D E
A B C D E
4 4
HTT for CPU sideA HTT for CPU sideB
Transmit power Receive power
and NB sideA Receive and NB sideA
power Transmit power
1D2V_S0 U62A 1D2V_HT0B_S0
D29 VLDT0_A VLDT0_B AH29 LAYOUT: Place bypass cap on topside of board near
D27 AH27
VLDT0_A VLDT0_B HTT power pins that are not connected directly to
1
1
1
1
1
D25 VLDT0_A VLDT0_B AG28
3 C289 C268 C273 C269 C28 AG26 C267 downstream HTT device, but connected internally to 3
SCD22U16V3ZY-GP SCD22U16V3ZY-GP SCD22U16V3ZY-GP SCD22U16V3ZY-GP VLDT0_A VLDT0_B SC4D7U10V5ZY-3GP
C26 AF29
other HTT power pins.
2
2
2
2
2
VLDT0_A VLDT0_B
B29 VLDT0_A VLDT0_B AE28
B27 VLDT0_A VLDT0_B AF25
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NB0CADOUT15 T25 N26 CPUCADOUT15 CPUCADOUT[15..0] 11
11 NB0CADOUT[15..0] NB0CADOUTJ15 L0_CADIN_H15 L0_CADOUT_H15 CPUCADOUTJ15
11 NB0CADOUTJ[15..0] R25 L0_CADIN_L15 L0_CADOUT_L15 N27 CPUCADOUTJ[15..0] 11
NB0CADOUT14 U27 L25 CPUCADOUT14
NB0CADOUTJ14 L0_CADIN_H14 L0_CADOUT_H14 CPUCADOUTJ14
U26 L0_CADIN_L14 L0_CADOUT_L14 M25
Used SideB Power Plane NB0CADOUT13 V25 L26 CPUCADOUT13 Used SideA Power Plane
NB0CADOUTJ13 L0_CADIN_H13 L0_CADOUT_H13 CPUCADOUTJ13
U25 L0_CADIN_L13 L0_CADOUT_L13 L27
NB0CADOUT12 W27 J25 CPUCADOUT12
NB0CADOUTJ12 L0_CADIN_H12 L0_CADOUT_H12 CPUCADOUTJ12
W26 L0_CADIN_L12 L0_CADOUT_L12 K25
NB0CADOUT11 AA27 G25 CPUCADOUT11
NB0CADOUTJ11 L0_CADIN_H11 L0_CADOUT_H11 CPUCADOUTJ11
AA26 L0_CADIN_L11 L0_CADOUT_L11 H25
NB0CADOUT10 AB25 G26 CPUCADOUT10
NB0CADOUTJ10 L0_CADIN_H10 L0_CADOUT_H10 CPUCADOUTJ10
AA25 L0_CADIN_L10 L0_CADOUT_L10 G27
NB0CADOUT9 AC27 E25 CPUCADOUT9
NB0CADOUTJ9 L0_CADIN_H9 L0_CADOUT_H9 CPUCADOUTJ9
AC26 L0_CADIN_L9 L0_CADOUT_L9 F25
NB0CADOUT8 AD25 E26 CPUCADOUT8
NB0CADOUTJ8 L0_CADIN_H8 L0_CADOUT_H8 CPUCADOUTJ8
AC25 L0_CADIN_L8 L0_CADOUT_L8 E27
NB0CADOUT7 T27 N29 CPUCADOUT7
NB0CADOUTJ7 L0_CADIN_H7 L0_CADOUT_H7 CPUCADOUTJ7
T28 L0_CADIN_L7 L0_CADOUT_L7 P29
NB0CADOUT6 V29 M28 CPUCADOUT6
NB0CADOUTJ6 L0_CADIN_H6 L0_CADOUT_H6 CPUCADOUTJ6
U29 L0_CADIN_L6 L0_CADOUT_L6 M27
NB0CADOUT5 V27 L29 CPUCADOUT5
NB0CADOUTJ5 L0_CADIN_H5 L0_CADOUT_H5 CPUCADOUTJ5
V28 L0_CADIN_L5 L0_CADOUT_L5 M29
NB0CADOUT4 Y29 K28 CPUCADOUT4
NB0CADOUTJ4 L0_CADIN_H4 L0_CADOUT_H4 CPUCADOUTJ4
W29 L0_CADIN_L4 L0_CADOUT_L4 K27
2 NB0CADOUT3 CPUCADOUT3 2
AB29 L0_CADIN_H3 L0_CADOUT_H3 H28
NB0CADOUTJ3 AA29 H27 CPUCADOUTJ3
NB0CADOUT2 L0_CADIN_L3 L0_CADOUT_L3 CPUCADOUT2
AB27 L0_CADIN_H2 L0_CADOUT_H2 G29
NB0CADOUTJ2 AB28 H29 CPUCADOUTJ2
NB0CADOUT1 L0_CADIN_L2 L0_CADOUT_L2 CPUCADOUT1
AD29 L0_CADIN_H1 L0_CADOUT_H1 F28
NB0CADOUTJ1 AC29 F27 CPUCADOUTJ1
NB0CADOUT0 L0_CADIN_L1 L0_CADOUT_L1 CPUCADOUT0
AD27 L0_CADIN_H0 L0_CADOUT_H0 E29
NB0CADOUTJ0 AD28 F29 CPUCADOUTJ0
L0_CADIN_L0 L0_CADOUT_L0
NB0HTTCLKOUT1 Y25 J26 CPUHTTCLKOUT1 CPUHTTCLKOUT1 11
11 NB0HTTCLKOUT1 NB0HTTCLKOUTJ1 L0_CLKIN_H1 L0_CLKOUT_H1 CPUHTTCLKOUTJ1
11 NB0HTTCLKOUTJ1 W25 L0_CLKIN_L1 L0_CLKOUT_L1 J27 CPUHTTCLKOUTJ1 11
NB0HTTCLKOUT0 Y27 J29 CPUHTTCLKOUT0 CPUHTTCLKOUT0 11
1D2V_HT0B_S0 11 NB0HTTCLKOUT0 NB0HTTCLKOUTJ0 L0_CLKIN_H0 L0_CLKOUT_H0 CPUHTTCLKOUTJ0
11 NB0HTTCLKOUTJ0 Y28 L0_CLKIN_L0 L0_CLKOUT_L0 K29 CPUHTTCLKOUTJ0 11
1 R141 2 49D9R2F-GPCPUHTTCTLIN1 R27 N25
R140 2 49D9R2F-GPCPUHTTCTLINJ1 L0_CTLIN_H1 L0_CTLOUT_H1
1 R26 L0_CTLIN_L1 L0_CTLOUT_L1 P25
NB0HTTCTLOUT T29 P28 CPUHTTCTLOUT0 CPUHTTCTLOUT0 11
11 NB0HTTCTLOUT NB0HTTCTLOUTJ L0_CTLIN_H0 L0_CTLOUT_H0 CPUHTTCTLOUTJ0
11 NB0HTTCTLOUTJ R29 L0_CTLIN_L0 L0_CTLOUT_L0 P27 CPUHTTCTLOUTJ0 11
62.10055.121
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