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5 4 3 2 1
SYSTEM DC/DC
Project code: 91.4CQ01.001 TPS51125 36
JM41/JM51 Discrete Block Diagram PCB P/N
REVISION
: 48.4CQ01.0SB
: 08274-1
INPUTS
DCBATOUT
OUTPUTS
5V_S5(6A)
3D3V_S5(5A)
D 5V_AUX_S5 D
UMA LVDS 3D3V_AUX_S5
PCB STACKUP
UMA CRT Switchable LVDS LCD
Thermal Sensor 19 RT8202 37
CLK GEN. Intel CPU DIS LVDS Graphic RGB CRT
TOP L1
SMSC ICS9LPRS365B Penryn SFF DIS CRT 40, 41 S L2 INPUTS OUTPUTS
EMC2103 27 3 VCC/GND L3
DCBATOUT 1D05V_S0(10A)
4,5,6 S L4
HOST BUS 38
VRAM(DDR3) VCC/GND L5 RT8202
667/800/[email protected]
4
64Mbx16x4 (512MB)
DDR3 Cantiga-GS SFF
57 GND/VCC L6 INPUTS OUTPUTS
MHz
800/1066 17,18 AGTL+ CPU I/F
S L7 DCBATOUT 1D5V_S3(11A)
DDR Memory I/F BOTTOM L8
PCIe x 16 RT9026 39
C
DDR3 INTEGRATED GRAHPICS
LVDS, CRT I/F
ATI M92-S2 CRT
C
800/1066 17,18
MHz CRT INPUTS OUTPUTS
7,8,9,10,11,12 BD
53,54,55,56 HDMI
X4 DMI 20 HDMI 5V_S5 DDR_VREF_S3
C-Link0
400MHz (1.2A)
CHARGER
23 LAN TXFM RJ45 MAX8731A 41
ICH9M SFF Giga LAN
Atheros AR8131
INT.SPKR 6 PCIe ports INPUTS OUTPUTS
1.5W PCI/PCI BRIDGE
Codec AZALIA ACPI 2.0 CHG_PWR
Int MIC Realtek DCBATOUT
4 SATA 18V 6.0A
ALC269Q 22 12 USB 2.0/1.1 ports
19 Mini 1 Card CPU DC/DC
ETHERNET (10/100/1000MbE)
MINI BD WLAN ADP3207A
B High Definition Audio PCIe x1 *3port 35 B
LPC I/F
Line Out USB 3 Port Mini 2 Card INPUTS OUTPUTS
Serial Peripheral I/F
Matrix Storage Technology(DO) 3G DCBATOUT
VCC_CORE
Active Managemnet Technology(DO)
25 0~1.3V
CRT 64A
MIC In
LPC BUS VGA
BD 13,14,15,16 ISL6263A
40
20
SATA INPUTS OUTPUTS
USB LPC
SATA CRT BD Camera KBC
Winbond DEBUG VCC_GFXCORE
HDD SATA 2 Port 20
17 WPCE773LA0DG SPI BIOS CONN. DCBATOUT
(7A)
28 (2MB)
29
A
SATA CARDREADER POWER BD MINI BD DIS A
ODD SATA BD 1 Port 26 3 Port 25
24 Touch INT. Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
USB Blue Tooth Pad 30 KB 28 Taipei Hsien 221, Taiwan, R.O.C.
SATA CARDREADER BD Title
24 MS/MS Pro/xD
SSD/HDD SATA 2 Port 24 /MMC/SD BLOCK DIAGRAM
Size Document Number Rev
Custom
21 JM41_Discrete -1
Date: Tuesday, April 07, 2009 Sheet 1 of 48
5 4 3 2 1
A B C D E
ICH9M Integrated Pull-up Cantiga chipset and ICH9M I/O controller
ICH9M Functional Strap Definitions Rev.1.5 page 92 Hub strapping configuration
Signal
ICH9 EDS 642879
and Pull-down Resistors Montevina Platform Design guide 22339
page 218
0.5
Usage/When Sampled Comment ICH9 EDS 642879 Rev.1.5
HDA_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 Pin Name Strap Description Configuration
PCIE Port Config1 bit1, pulled low.When TP3 not pulled low at rising edge SIGNAL Resistor Type/Value
Rising Edge of PWROK of PWROK,sets bit1 of RPC.PC(Config Registers: CL_CLK[1:0] PULL-UP 20K CFG[2:0] FSB Frequency 000 = FSB1067
offset 224h). This signal has weak internal pull-down Select 011 = FSB667
CL_DATA[1:0] PULL-UP 20K 010 = FSB800
others = Reserved
4 HDA_SYNC PCIE config1 bit0,
Rising Edge of PWROK.
This signal has a weak internal pull-down.
Sets bit0 of RPC.PC(Config Registers:Offset 224h)
CL_RST0# PULL-UP 20K
CFG[4:3] Reserved
4
DPRSLPVR/GPIO16 PULL-DOWN 20K CFG8
GNT2#/ PCIE config2 bit2, This signal has a weak internal pull-up. CFG[15:14]
GPIO53 Rising Edge of PWROK. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) ENERGY_DETECT PULL-UP 20K CFG[18:17]
GPIO20 Reserved This signal should not be pulled high. HDA_BIT_CLK PULL-DOWN 20K
CFG5 DMI x2 Select 0 = DMI x2
GNT1#/ ESI Strap (Server Only) ESI compatible mode is for server platforms only. HDA_DOCK_EN#/GPIO33 PULL-UP 20K 1 = DMI x4 (Default)
GPIO51 Rising Edge of PWROK This signal should not be pulled low for desttop CFG6 iTPM Host 0= The iTPM Host Interface is enabled(Note2)
and mobile. HDA_RST# PULL-DOWN 20K Interface 1=The iTPM Host Interface is disalbed(default)
HDA_SDIN[3:0] PULL-DOWN 20K 0 = Transport Layer Security (TLS) cipher
Top-Block Sampled low:Top-Block Swap mode(inverts A16 for CFG7 Intel Management suite with no confidentiality
GNT3#/ Swap Override. all cycles targeting FWH BIOS space). HDA_SDOUT PULL-DOWN 20K engine Crypto strap 1 = TLS cipher suite with
GPIO55 Rising Edge of PWROK. Note: Software will not be able to clear the confidentiality (default)
Top-Swap bit until the system is rebooted HDA_SYNC PULL-DOWN 20K
0 = Reverse Lanes,15->0,14->1 ect..
without GNT3# being pulled down. GLAN_DOCK# The pull-up or pull-down active when configured for native CFG9 PCIE Graphics Lane 1= Normal operation(Default):Lane
GLAN_DOCK# functionality and determined by LAN controller
Numbered in order
GNT0#: Boot BIOS Destination Controllable via Boot BIOS Destination bit GNT[3:0]#/GPIO[55,53,51] PULL-UP 20K
SPI_CS1#/ Selection 0:1. (Config Registers:Offset 3410h:bit 11:10). 0 = Enable (Note 3)
GPIO58 Rising Edge of PWROK. GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. GPIO[20] PULL-DOWN 20K CFG10 PCIE Loopback enable 1= Disabled (default)
Integrated TPM Enable, Sample low: the Integrated TPM will be disabled. GPIO[49] PULL-UP 20K 00 = Reserve
Rising Edge of CLPWROK Sample high: the MCH TPM enable strap is sampled CFG[13:12] XOR/ALL 10 = XOR mode Enabled
SPI_MOSI low and the TPM Disable bit is clear, the LDA[3:0]#/FHW[3:0]# PULL-UP 20K 01 = ALLZ mode Enabled (Note 3)
Integrated TPM will be enable. 11 = Disabled (default)
LAN_RXD[2:0] PULL-UP 20K
3 DMI Termination Voltage, The signal is required to be low for desktop LDRQ[0] PULL-UP 20K
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default) 3
Rising Edge of PWROK. applications and required to be high for
GPIO49 mobile applications. LDRQ[1]/GPIO23 PULL-UP 20K 0 = Normal operation(Default):
CFG19 DMI Lane Reversal Lane Numbered in Order
PME# PULL-UP 20K
1 = Reverse Lanes
PCI Express Lane Signal has weak internal pull-up. Sets bit 27 PWRBTN# PULL-UP 20K DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3)
SATALED# Reversal. Rising Edge of MPC.LR(Device 28:Function 0:Offset D8) DMI x2 mode[MCH -> ICH]:(3->0,2->1)
of PWROK. SATALED# PULL-UP 15K
SPKR No Reboot. If sampled high, the system is strapped to the SPI_CS1#/GPIO58/CLGPIO6 PULL-UP 20K Digital Display Port 0 = Only Digital Display Port
Rising Edge of PWROK. "No Reboot" mode(ICH9 will disable the TCO Timer (SDVO/DP/iHDMI) or PCIE is operational (Default)
system reboot feature). The status is readable SPI_MOSI PULL-DOWN 20K CFG20 Concurrent with PCIe 1 =Digital display Port and PCIe are
via the NO REBOOT bit. operting simulataneously via the PEG port
SPI_MISO PULL-UP 20K
0 =No SDVO Card Present (Default)
TP3 XOR Chain Entrance. This signal should not be pull low unless using SPKR PULL-DOWN 20K SDVO_CTRLDATA SDVO Present
Rising Edge of PWROK. XOR Chain testing. 1 = SDVO Card Present
TACH_[3:0] PULL-UP 20K
0 = LFP Disabled (Default)
GPIO33/ Flash Descriptor Sampled low:the Flash Descriptor Security will be TP[3] PULL-UP 20K Local Flat Panel
HDA_DOCK Security Override Strap overridden. If high,the security measures will be L_DDC_DATA (LFP) Present 1= LFP Card Present; PCIE disabled
_EN# Rising Edge of PWROK in effect.This should only be enabled in manufacturing USB[11:0][P,N] PULL-DOWN 15K
environments using an external pull-up resister.
NOTE:
1. All strap signals are sampled with respect to the leading edge of
the (G)MCH Power OK (PWROK) signal.
2. iTPM can be disabled by a 'Soft-Strap' option in the
2 Flash-decriptor section of the Firmware. This 'Soft-Strap' is 2
activated only after enabling iTPM via CFG6.
Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.
1 DIS
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reference
Size Document Number Rev
A3
JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 2 of 48
A B C D E
1D05V_S0 3D3V_S0
3D3V_S0 R215
R220 R222
1 2 1D05V_CLK_S0
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1 2 3D3V_48MPW R_S0 C522 C516 C508 C512 C515 C532 3D3V_CLK_S0 1 2
1
1
1
1
1
1
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
C525 C541 C517 C507 C526 C548 C549
0R0603-PAD
1
1
1
1
1
1
1
1
1
SC1U10V3KX-3GP
SC4D7U10V5ZY-3GP
C523 C524
0R0603-PAD 0R0603-PAD
SC4D7U6D3V3KX-GP
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
DY
4 4
3D3V_48MPW R_S0
C579
3D3V_CLK_S0 1D05V_CLK_S0
1 2
3D3V_S0
R210
R209 SC27P50V2JN-2-GP
2
U35
16
46
62
23
19
27
43
52
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