Service Manuals, User Guides, Schematic Diagrams or docs for : acer Acer_TM800x_Quanta_ZI6
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1 2 3 4 5 6 7 8
PIRQ# REQ#/GNT# IDSEL
DC/DC BATT SELECTOR
ZI6 BLOCK DIAGRAM @:ZI66 Internal Gra.
#:ZI68 External Gra.
VGA
CARDBUS
IEEE 1394
X
C, (B)
B
X
3
2
X
22
23
PG 37
CENTRINO
1.25VDDR MINI-PCI E, F 1 20
2.5VDDR LAN D 0 18
BATT CHARGER CLOCKS USB 2.0 X X X
A AC/BATT A
PG 31 CONNECTOR PG 36
1.5V/1.8V Banias/Dothan PG 12
Port Replicator
PG 32 CPU CORE
System Power R
PG 33
MAX1632 (Micro-FCPGA) LVDS Panel Connector PS2 X2
PG 34 1S1P
PG 3,4 LINE-IN
R LINE-OUT
+2.5V
LVDS MICROPHONE-IN
DDR-SODIMM1 4X100MHZ Video USB 1.1 X2
Controller DVI CRT
PG 10 +1.5V S-VIDEO
ATI M11CSP64
AGP 1.5V, 66MHz VGA_CORE(+1.2V) TV out LAN
Montara-GM+
DDR-SODIMM2 +1.8V
266/200 MHZ DDR
R PG 30
PG 10 CRT port
TV out DVI R.G,B
B
732 Micro-FCBGA R B
PG 5,6,7
R
DDR-Termiation Chrontel 7009
PG 11 66(266)MHZ, 1.8V DVOB
HUB I/F TV EN-CONDE
Primary IDE ATA 66/100 ICH4-M
HDD PG 17 421 BGA R.G,B
Secondary IDE - Swap Bay PG 8,9
(Optical Drive, 2ND HDD)
PG 17
C C
USB 2.0
4-IN-1 SLOT
PG 19
33MHZ, 3.3V PCI
USB connec*4
PG 28 AC LINK LAN MINI-PCI CARDBUS IEEE-1394
3.3V LPC, 33MHz USB 1.1 BCM5705M SOCKET OZ711EC1 TSB43AB21
PG 22 PG 21 PG 18 PG 20
LED/B MDC
Connector CONNECTOR
CARDBUS SLOT
PG 19 PG 21 RJ11 RJ45 CALEXICO 1394 CONN.
AC LINK SCR SLOT
SIO PC87391 PC87591 PG 16 PG 21 PG 18 PG 20
100 Pins TQFP 176 Pins LQFP
HEAD PHONE
D
AUDIO AUDIO
D
PG 26 CODEC AMP
LINE IN
TPA0312
PG 25
EXT. /INT.
MIC QUANTA
PG 24
PG 24, 25
Title
COMPUTER
Schematic Block Diagram1
FIR Parallel Touchpad Keyboard FLASH FAN 1,2
PG 26 PG 26 PG 19 PG 29 PG 27 PG 29 Size Document Number R ev
C
ZI6
Date: Monday, January 12, 2004 Sheet 1 of 43
1 2 3 4 5 6 7 8
3 2 1
PU8
PU1
MAX1632 ALWAYS ON VOLTAGE
SC1565
VL EN 3V_591
2.5VSUS VIN VOUT +1.8V
5VPCU
CTRL
C
12VOUT MAINON C
PQ10 NPN + PQ9 PMOS
PU4
SC1486 12VOUT VIN VOUT +12V
5VSUS EN 2.5VSUS
7.5A CTRL
MAINON
PQ5 SI5402
SMDDR_VTERM NMOS
3A
1.5V_S5 VIN VOUT +1.5V
PU3
MAX1844 CTRL
S5_ON EN 1.5V_S5 MAIND
B B
PQ4 SI9936
PQ40 SI9936
2-NMOS
2-NMOS PQ11 NPN
PQ39 NPN
S5_LAN E G S LANVCC
G S 3V_S5
S5_ON E S3_MODEM E G S 3V_MODEM
S 5V_S5
G D D
D D PQ12 NPN
3V_591 3V_591
3V_591 5VPCU
PQ3 SI9936
PU6
2-NMOS
MAX1907
MAIND G S +3V
VRON EN VCC_CORE
25A G S +2.5V
D D SUSON V TRANS CIRCUIT SUSD
3V_591 2.5VSUS
PU2 PQ1 SI9936
A SC338 2-NMOS A
MAINON V TRANS CIRCUIT MAIND
PQ38 SI9936
5VSUS VIN DRV1 G S VTT 2-NMOS
(1.05V)
MAIND G S +5V
CTRL
DRV2 G
D
S 1.2VCCT QUANTA
SUSD G S 5VSUS COMPUTER
D D Title
VRON 1.5V_S5 POWER BLOCK DIAGRAM
5VPCU 5VPCU Size Document Number R ev
C
ZI6
Date: Monday, January 12, 2004 Sheet 2 of 43
3 2 1
1 2 3 4 5 6 7 8
+3V
R325 150/F
+5V +3V
2
HD#[0..63]
U21A HD#[0..63] <5>
C415
HA#[3..31] R330 R328 0.1U/50V
<5> HA#[3..31]
1
HA#3 P4 A19 HD#0
A3# D0#
2
HA#4 U4 A25 HD#1 10K 10K U26
HA#5
HA#6
V3
A4#
A5#
Banias D1#
D2# A22 HD#2
HD#3 MBDATA THDAT_SMB THCLK_SMB
R3 A6# D3# B21 <23,31> MBDATA 3 1 8 SMCLK VCC 1
A HA#7 V2 A24 HD#4 THERMDA A
HA#8 A7# D4# HD#5 THDAT_SMB
W1 A8# 1 OF 3 D5# B26 7 SMDATA DXP 2
HA#9 T4 A21 HD#6 Q37
HA#10 A9# D6# HD#7 RHU002N06 T117 C407
W2 A10# D7# B20 6 -ALT DXN 3
HA#11 Y4 C20 HD#8 +5V 2200P
HA#12 A11# D8# HD#9 *PAD THERMDC
Y1 A12# D9# B24 5 GND -OVT 4
HA#13 U1 D24 HD#10
HA#14 A13# D10# HD#11 MAX6648 R324 1K
AA3 A14# D11# E24 For ATE
2
HA#15 Y3 C26 HD#12 2 1 +3V
HA#16 A15# D12# HD#13
AA2 A16# D13# B23
HA#17 AF4 E23 HD#14 MBCLK 3 1 THCLK_SMB
A17# D14# <31,42> MBCLK 6648_OVT# <33>
HA#18 AC4 C25 HD#15
HA#19 A18# D15# HD#16
AC7 A19# D16# H23
HA#20 AC3 G25 HD#17 Q35
HA#21 A20# D17# HD#18 RHU002N06
AD3 A21# D18# L23
HA#22 AE4 M26 HD#19
HA#23 A22# D19# HD#20
AD2 A23# D20# H24
HA#24 AB4 F25 HD#21
HA#25 A24# REQUEST DATA D21# HD#22
AC6 A25# D22# G24
HA#26 AD5 PHASE PHASE J23 HD#23
HA#27 A26# D23# HD#24
AE2 SIGNALS SIGNALS M23
HA#28 A27# D24# HD#25
AD6 A28# D25# J25
HA#29 AF3 L26 HD#26 +3V +3V
HA#30 A29# D26# HD#27 VTT
AE1 A30# D27# N24
HA#31 AF1 M25 HD#28
A31# D28# HD#29
D29# H26
2
N25 HD#30
D30# HD#31 R336 R337
D31# K25
U3 Y26 HD#32 IERR# R520 56
<5> HADSTB0# ADSTB0# D32# *2K/F
AE5 AA24 HD#33 CPUPWRGD R519 330 330
<5> HADSTB1# ADSTB1# D33#
T25 HD#34 VTT
D34#
1
B U23 HD#35 TCK R322 27.4/F ICH_THRM# B
D35# ICH_THRM# <9,33>
R2 V23 HD#36 TRST# R516 680
<5> HREQ#0 REQ0# D36#
3
P3 R24 HD#37
<5> HREQ#1 REQ1# D37#
T2 R26 HD#38 R333 2
<5> HREQ#2 REQ2# D38#
P1 R23 HD#39
<5> HREQ#3 REQ3# D39#
3
T1 AA23 HD#40 56/F Q44
<5> HREQ#4 REQ4# D40#
1
U26 HD#41 R332 Q40
D41#
D42# V24 HD#42 R516 should CPU_PROCHOT# 2 1 2 *RHU002N06
N2 ERROR U25 HD#43 *MMBT3904
<5> ADS# ADS# D43#
SIGNALS
D44# V26
Y23
HD#44
HD#45
be place *330
D45#
1
HD#46
IERR# A4
D46# AA26
Y25 HD#47 within 2" of
IERR# D47# HD#48
AB25
<5> HBREQ0# N4 BREQ0#
D48#
D49# AC23 HD#49 the processor ;
J3 ARBITRATION AB24 HD#50
<5> BPRI# BPRI# D50#
<5> BNR# L1
J2
BNR#
PHASE
SIGNALS
D51# AC20
AC22
HD#51
HD#52
others place
<5> HLOCK# LOCK# D52# HD#53
K3
D53# AC25
AD23 HD#54
near ITP
<5> HIT# HIT# D54#
K4 SNOOP PHASE AE22 HD#55
<5> HITM# HITM# D55#
L4 SIGNALS AF23 HD#56
<5> DEFER# DEFER# D56#
AD24 HD#57
BPM0# D57# HD#58
C8 BPM0# D58# AF20
BPM1# B8 RESPONSE AE21 HD#59
BPM2# BPM1# PHASE D59# HD#60 VTT VTT
A9 BPM2# D60# AD21
BPM3# C9 SIGNALS AF25 HD#61 +3V
BPM3# D61# HD#62
<5> HTRDY# M3 TRDY# D62# AF22
H1 AF26 HD#63
<5> RS#0 RS0# D63#
<5> RS#1 K1 RS1#
L2 R440 R435 R431 R428
C <5> RS#2 RS2# C
R443
A20M# C2 C23 54.9/F *54.9/F 39.2/F 150
<8> A20M# A20M# DSTBN0# HDSTBN0# <5>
FERR# D3 PC C22 150
<8> FERR# FERR# DSTBP0# HDSTBP0# <5>
IGNNE# A3 COMPATIBILITY K24
<8> IGNNE# IGNNE# DSTBN1# HDSTBN1# <5>
R513 0 R_CPUPWRGD E4 SIGNALS L24
<9> CPUPWRGD PWRGOOD DSTBP1# HDSTBP1# <5>
SMI# B4 W25 TDI DBR#
<8> SMI# SMI# DSTBN2# HDSTBN2# <5>
W24 TMS
DSTBP2# HDSTBP2# <5>
TCK A13 AE24
TCK DSTBN3# HDSTBN3# <5>
TDO A12 DIAGNOSTIC AE25
TDO DSTBP3# HDSTBP3# <5>
TDI C12 & TEST BPM0# T120 *PAD
TMS TDI
C11 SIGNALS
TRST# TMS TDO BPM1# T121 *PAD
B13 TRST# DBI0# D25 HDBI0# <5>
T29 *PAD A16 ITP_CLK0 DBI1# J26 HDBI1# <5>
T28 *PAD A15 T24 BPM2# T122 *PAD
ITP_CLK1 DBI2# HDBI2# <5>
PREQ# B10 AD20
PREQ# DBI3# HDBI3# <5>
P RDY# A10 CPURST# BPM3# T124 *PAD
DBR# PRDY#
<9> DBR# A7 DBR# DBSY# M2 DBSY# <5>
H2 P RDY# T125 *PAD
DRDY# DRDY# <5>
<8> INTR D1 LINT0
D4 EXECUTION PREQ# T126 *PAD
<8> NMI LINT1
STPCLK# C6 CONTROL B14
<8> STPCLK# STPCLK# BCLK1 HCLK_CPU# <12>
CPUSLP# A6 SIGNALS B15 Del ITP700
<8> CPUSLP# SLP# BCLK0 HCLK_CPU <12>
DPSLP# B7
<6,8> DPSLP# DPSLP#
Del R434,R439,C542,R442
THERMDA B18 B5 CPUINIT#
THERMDA INIT# CPUINIT# <8>
THERMDC A18 THERMDC R_CPURST# R515 0
RESET# B11 CPURST# <5>
THERMTRIP# C17
<9> THERMTRIP# THERMTRIP# THERMAL DIODE C19
DPWR# DPWR# <6>
CPU_PROCHOT# B17
D PROCHOT# D
Banias_Processor
QUANTA
Title
COMPUTER
Banias Processor (HOST)
Size Document Number R ev
C
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