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A B C D E
Compal confidential Block Diagram
Model Name : CY23 LA-1281 Rev1.0
1 1
INTEL FC-PGA370
APICCLK
CRT
HCLK_CPU
Connector Page 2,3
page 14
HA#(3..31) HD#(0..63) Y1
14.318MHZ
TV_OUT 14MOSC
HCLK_NB
Connector Twister PN-133T Clock Generator 14MCRT/14.3M_TV
page 13 PCLK_NB
(VT8606)PCIGNT#/PCIREQ#
DCLKWR
ICS 9248-195
page 11
PCLK_1394
PCLK_PCM
page 4,5,6 PIRQA# DCLKO
PCLK_MINI
MA(0..13)
CLK_SDRAM0
MD(0..63)
TFT Panel CLK_SDRAM2,3
Interface
2 page 14 2
On Board
AD(0..31)
Memory Damping 64/128MB SO-DIMM 0
Resistor (Bank 2,3)
page 6 (Bank 0) page 8
PCLK_SB
page 7
PCI BUS
USB Port 0,1
Mini PCI CardBus FIR DIRECT
IEEE 1394 VT686B 48MHZ
CD-PLAY
Socket
PIRQB#/PIRQD#
OZ6933 PIRQC#
GNT#2/REQ#2
AC97 page 25
page 9,10
14MOSC
FUNCTION
GNT#0/REQ#0
GNT#1/REQ#1
page 23 AD27/AD28
PIRQA#/PIRQB#
page 15
GNT#3/REQ#3
AD15 page 29
AD24
Interface IDE CHANNEL 1 page 18
page 27
3
SA(0..15)
Pull Up/Down 3
Slot 0&1 Slot 0 SD(0..15) Resistor
page 29
page 16
ISA BUS IDE Damping page 12
Power On/Off Resistor
Reset Circuit page 17
page 28
KeyBoard
87570
page 20 IDE Connector PIO
page 24
(FDD/HDD/CR-ROM)
DC/DC Interface
RTC Battery page 19
page 22
I/O Buffer KBD
page 21 page 21
4 4
Power Circuit BIOS Touch Pad
DC/DC page 21 page 26
page
30,31,32,33
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND SCHEMATIC, M/B LA-1281
PROPRIETARY NOTE TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE 401202
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. , 22, 2001
Date: Sheet 1 of 34
A B C D E
A B C D E
+5VS
HA#[3..31] HD#[0..63]
4 HA#[3..31] U38A HD#[0..63] 4
1
HA#3 AK8 W1 HD#0 R90
A3# D0#
1
HA#4 HD#1 200
HA#5
AH12
AH8
A4# FC-PGA2 D1# T4
N1 HD#2 C79
HA#6 A5# D2# HD#3 .1UF
AN9 A6# D3# M6
HA#7 HD#4
2
2
AL15 A7# D4# U1
HA#8 AH10 S3 HD#5 1617VCC
HA#9 A8# D5# HD#6
AL9 A9# D6# T6
HA#10 HD#7 U6
AH6 A10# D7# J1
1
4
VCMOS VCMOS +3VS HA#11 AK10 S1 HD#8 C80 1 16 from 87570 4
HA#12 A11# D8# HD#9 NC NC
AN5 A12# D9# P6 2 VCC STBY 15
HA#13 AL7 Q3 HD#10 2200PF THERMDA 3 14
A13# D10# DXP SMBCLK SMC 18,20,24
HA#14 HD#11 THERMDC
2
2 AK14 A14# D11# M4 4 DXN NC 13
2
2
HA#15 AL5 Q1 HD#12 5 12
A15# D12# NC SMBDATA SMD 18,20,24
R64 R67 R73 HA#16 AN7 L1 HD#13 6 11
1.5K 1.5K 10K HA#17 A16# D13# HD#14 ADD1 ALERT
AE1 A17# D14# N3 7 GND ADD0 10
HA#18 Z6 U3 HD#15 8 9
HA#19 A18# D15# HD#16 GND NC
AG3 A19# D16# H4
HA#20 HD#17 MAX1617
1
21
1
AC3 A20# D17# R4 ATF# 21
HA#21 AJ1 P4 HD#18
HA#22 A21# D18# HD#19
AE3 A22# D19# H6
FERR#1.5 3 1 HA#23 AB6 L3 HD#20
FERR# 9 A23# D20#
1
1
HA#24 AB4 G1 HD#21
HA#25 A24# D21# HD#22 R89 R96
AF6 A25# D22# F8
HA#26 Y3 G3 HD#23 1K 1K
Q5 A26# D23#
HA#27 AA1 REQUEST DATA K6 HD#24
HA#28 A27# D24# HD#25
FDV301N AK6 A28# PHASE PHASE D25# E3 9,27,32 VR_POK 1 2 PWRGD_CPU 1 2 +2.5V_CLK
HA#29 HD#26 R27 180
2
2
Z4 A29# SIGNALS SIGNALS D26# E1
HA#30 AA3 F12 HD#27 D7 1 2
HA#31 A30# D27# HD#28 RB751V R395 @1.8K
AD4 A31# D28# A5
X6 A3 HD#29 +5VS CPU_IO
A32# D29# HD#30
AC1 A33# D30# J3
W3 C5 HD#31
A34# D31# HD#32
AF4 A35# D32# F6
C1 HD#33
HREQ#0 D33# HD#34
4 HREQ#0 AK18 REQ0# D34# C7
HREQ#1 AH16 B2 HD#35 BREQ0# 8 1 HA#5 8 1 HD#39 1 8 HD#1 8 1
4 HREQ#1 REQ1# D35#
HREQ#2 AH18 C9 HD#36 RS#2 7 2 HA#13 7 2 HD#36 2 7 HD#5 7 2
4 HREQ#2 REQ2# D36#
3 HREQ#3 AL19 A9 HD#37 DBSY# 6 3 HA#10 6 3 HD#37 3 6 HD#8 6 3 3
4 HREQ#3 REQ3# D37#
HREQ#4 AL17 D8 HD#38 DRDY# 5 4 HA#12 5 4 HD#38 4 5 HD#17 5 4
4 HREQ#4 REQ4# D38#
AN23 D10 HD#39
RP# D39# HD#40 RP2 RP6 RP43 RP25
D40# C15
ADS# AN31 D14 HD#41 @8P4R-56 @8P4R-56 @8P4R-56 @8P4R-56
4 ADS# ADS# D41#
D12 HD#42 HA#16 8 1 HD#27 1 8 HD#0 8 1
D42# HD#43 HA#15 HD#42 HD#4
D43# A7 7 2 2 7 7 2
AK24 A11 HD#44 HA#28 6 3 HD#45 3 6 HD#15 6 3
AERR# ERROR D44# HD#45 HA#31 HD#44 HD#6
AL11 AP0# D45# C11 RP26 5 4 4 5 5 4
AN13 SIGNALS A21 HD#46 IGNNE# 1 8
AP1# D46# VCMOS
V4 A15 HD#47 A20M# 2 7 RP14 RP44 RP24
BERR# D47# HD#48 INTR @8P4R-56 @8P4R-56 @8P4R-56
B36 BINIT# D48# A17 3 6
AE35 C13 HD#49 NMI 4 5 HA#19 8 1 HD#40 1 8 HD#12 8 1
IERR# D49# HD#50 HA#25 HD#41 HD#10
D50# C25 7 2 2 7 7 2
BREQ0# HD#51 8P4R-150 HA#22 HD#49 HD#9
4 BREQ0# AN29 BR0# D51# A13 6 3 3 6 6 3
BPRI# AN17 D16 HD#52 PRDY# 1 2 HA#17 5 4 HD#51 4 5 HD#18 5 4
4 BPRI# BPRI# D52#
BNR# AH14 ARBITRATION A23 HD#53 R151 150
4 BNR# BNR# D53#
LOCK# AK20 PHASE C21 HD#54 SLP# 1 2 RP20 RP45 RP28
4 HLOCK# LOCK# D54#
X2 SIGNALS C19 HD#55 R54 150 @8P4R-56 @8P4R-56 @8P4R-56
BR1#/RSVD* D55# HD#56 CPUINIT# HA#23 HD#48 HD#14
D56# C27 1 2 8 1 1 8 8 1
HIT# AL25 A19 HD#57 R61 150 HA#24 7 2 HD#63 2 7 HD#2 7 2
4 HIT# HIT# D57#
HITM# AL23 SNOOP PHASE C23 HD#58 STPCLK# 1 2 HA#20 6 3 HD#52 3 6 HD#3 6 3
4 HITM# HITM# D58#
DEFER# AN19 SIGNALS C17 HD#59 R53 150 HA#27 5 4 HD#47 4 5 HD#11 5 4
4 DEFER# DEFER# D59#
A25 HD#60 FLUSH# 1 2
D60# HD#61 R57 150 RP19 RP46 RP27
G33 BP2# D61# A27
E37 RESPONSE E25 HD#62 SMI# 1 2 @8P4R-56 @8P4R-56 @8P4R-56
BP3# D62# HD#63 R47 150 HA#30 HD#46 HD#13
C35 BPM0# PHASE D63# F16 8 1 1 8 8 1
E35 SIGNALS PREQ# 1 2 HA#29 7 2 HD#55 2 7 HD#20 7 2
HTRDY# BPM1# R127 330 HA#18 HD#57 HD#7
4 HTRDY# AN25 TRDY# 6 3 3 6 6 3
2 RS#0 HA#26 HD#59 HD#16 2
4 RS#0 AH26 RS0# DEP0# C33 5 4 4 5 5 4
RS#1 AH22 C31
4 RS#1 RS1# DEP1#
RS#2 AK28 A33 CPURST# 1 2 RP22 RP47 RP31
4 RS#2 RS2# DEP2#
AC37 A31 R26 56.2_1% CPU_IO @8P4R-56 @8P4R-56 @8P4R-56
RSP# DEP3# ADS# HREQ#2 HD#50 HD#19
DEP4# E31 1 2 8 1 1 8 8 1
A20M# AE33 C29 R7 @56.2_1% HREQ#0 7 2 HD#58 2 7 HD#24 7 2
3 A20M# A20M# DEP5#
FERR#1.5 AC35 PC E29 HREQ#4 6 3 HD#53 3 6 HD#30 6 3
IGNNE# FERR# DEP6# BPRI# HD#54 HD#22
3 IGNNE# AG37 IGNNE# COMPATIBILITY DEP7# A29 5 4 4 5 5 4
PWRGD_CPU AK26 SIGNALS
SMI# PWRGOOD DBSY# RP9 RP48 RP30
9 SMI# AJ35 SMI# DBSY# AL27 DBSY# 4
AN27 DRDY# @8P4R-56 @8P4R-56 @8P4R-56
DRDY# DRDY# 4
AN37 RS#1 8 1 HD#61 1 8 HD#43 1 8
TDO DIAGNOSTIC HLOCK# HD#56 HD#34
1 8 AN35 TDI 7 2 2 7 2 7
2 7 AK32 & TEST HREQ#3 6 3 HD#62 3 6 HD#32 3 6
TMS DEFER# HD#60 HD#28
3 6 AN33 TRST# SIGNALS 5 4 4 5 4 5
6 BSEL0 4 5 PWRGD_CPU AL33 TCK
PREQ# J37 J33 RP10 RP49 RP42
6,11 BSEL1 PREQ# PICCLK APICCLK 11
RP98 PRDY# A35 L35 @8P4R-56 @8P4R-56 @8P4R-56
PRDY# PICD1 VCMOS
+3VS 2 1 R6 1K 8P4R-1K AJ33 BSEL0 PICD0 J35 R117 150 RS#0 8 1 HA#4 8 1 HD#31 1 8
2 1 R5 1K AJ31 BSEL1
R131 150 HIT# 7 2 HA#8 7 2 HD#25 2 7
2 1 R10 @1K
INIT# AG33 CPUINIT#
CPUINIT# 9
HTRDY# 6 3 HA#11 6 3 HD#29 3 6
INTR M36 AE37 FLUSH# HITM# 5 4 HA#9 5 4 HD#35 4 5
3 INTR INTR/LINT0 FLUSH#
NMI L37 EXECUTION AH4 CPURST#
3 NMI NMI/LINT1 RESET# CPURST# 4,9
STPCLK# AG35 CONTROL X4 RP11 RP7 RP41
9 STPCLK# STPCLK# RESET2#/VSS*
SLP# AH30 SIGNALS W37 R94 1K @8P4R-56 @8P4R-56 @8P4R-56
9 SLP# SLP# BCLK HCLK_CPU 11
1
C533 reserve for HREQ#1 8 1 HA#3 8 1 HD#23 1 8
Intel Celeron THERMDA AL31 AG1 1 2 C94 HA#7 7 2 HA#6 7 2 HD#21 2 7
C139 THERMDC THERMDA THERMAL DIODE EDGCTRL/VTT* R396 1K BNR# HA#21 HD#26
,VIA recommend AL29 THERMDC 2 1 1 2 6 3 6 3 3 6
3
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