Service Manuals, User Guides, Schematic Diagrams or docs for : acer Acer_Travelmate_5744_BIC50_BA52_CP
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5 4 3 2 1
PEGATRON CONFIDENTIAL
MODEL NAME :
D
PCB NO : D
69- P/N :
C C
BA52_CP Colay Schematic
Intel Arrandale rPGA-989
PCH BGA 1071
2011-0503
B B
REV :R2.0
A A
Title : Cover Page
BU1-RD Div.1-HW RD Dept.1 Engineer: Elmer Chiu
Size Project Name Rev
Custom
BIC50 2.0
Date: W ednesday, May 18, 2011 Sheet 1 of 77
5 4 3 2 1
5 4 3 2 1
BA52_CP BLOCK DIAGRAM
CLOCK GEN.
D SLG8SP585V D
ARD DDR3 1066 MHz DDR-III PAGE 24
(989-Pin rFCPGA)
SO-DIMM
PAGE 21,22
PAGE 7-12
DMI
SPI 32Mb PCIE *1 10/100 LAN LAN IO
PAGE 13 BCM57780
LED Switch
PAGE 66 PAGE 65
PAGE 67, 68
CRT
PAGE 38
POWER
LVDS & INV
PCH MiniCard CPU VCORE
1071 BGA PAGE 80
WLAN/WMAX
C PAGE 37 C
PAGE 55 SYSTEM, +3V, +5V
Azalia PAGE 81
FFC +VCCP & +VCCP_VT
HP_OUT PAGE 82
PAGE 67
Azalia Codec
DDR & VTT
FFC
RTK/ALC271 LPC PAGE 83
MIC IN
PAGE 41 42
PAGE 13-19
PAGE 67 Card Reader 2.5V & 1.5VS &1.1VS
PAGE 84
RTS5138
PAGE 50
SATA PORT SMART CHARGER
PAGE 88
USB2.0
SATA P0
SATA P1 HDD POWER DETECT
K/B EC PAGE 90
USB2.0
PAGE 48 SATA P4 ODD
SATA
PCH SPI 32Mb IT8518E SATA P5 LOAD SWITCH
PAGE 91
PAGE 13
PAGE 46 PCIe Port POWER PROTECT
B
SPI128Kb Camera B
PCIE_P1 PAGE 92
PAGE 30 PAGE 37
PCIE_P2 Mini CARD (WLAN)
T/P
PCIE_P3
PAGE 48 Power Rails
PCIE_P4 USB3.0 Controller
Sleep State RTC VA VSUS V VS
SMBus PCIE_P5
FAN SATA HDD PCIE_P6 LAN
S0 ON ON ON ON ON
S3 ON ON ON ON OFF
PAGE 60
PAGE 49 USB2.0 USB PORT S4 ON ON ON OFF OFF
USB x3 Ports
USB P00 Card Reader
SATA ODD PAGE 61, 67
S5/ AC ON ON ON OFF OFF
USB P01 S5/ DC ON ON OFF OFF OFF
PAGE 60
USB P02
USB P03
USB P04
USB P05
A USB P08 WiFi A
USB P09 External Entry
USB P10 Camera
USB P11 External Main
USB P12 External Main
Title : BLOCK DIAGRAM
BU1-RD Div.1-HW RD Dept.1 Engineer: Elmer Chiu
USB P13 External Main/Entry
Size Project Name Rev
Custom
BIC50 2.0
Date: Tuesday, May 03, 2011 Sheet 2 of 77
5 4 3 2 1
A B C D E
SCHEMATIC INDEX V1.0
PAGE# Description NOTE PAGE# Description NOTE
1 01 Cover Page 69 3D sensor 1
02 Block Diagram 70 CAP sense
03 PAGE INDEX 71 FM tunner
04 Bus connection 72 SCREW PAD
05 SMBus Diagram 73 NAND FLASH/ HYPER FLASH
06 Power Rail 74 Reserved
07-10 CPU 75 XDP
11-16 GMCH 76 Port Docking
2 2
17-20 ICH 77 DC-IN & BAT connector and discharge
21-23 DDR2/3 SO-DIMM 78 Power Sequence Logic
24 Clock Generator 79 POWER LOAD SWITCH
25-33 Reserved 80-100 POWER schematics
34 Power Express/ SLI Logic 101- Daughter Board Combined Solutions
35-36 Reserved VGA port
37 LVDS CON
38 RGB CON
3 3
39 HDMI (Level shift for UMA)
40 Dispaly port
41-45 AUDIO CODEC & AMP & Jack
46-48 EC ITE8512E / FLASH / KB / TP
49 THERMAL / FAN
50-52 CARD READER / 1394
53 Smart Card
4 54 PCI-Express Card 4
55 MINI CARD -WUSB /UPCONVERT
56 MINI CARD -WWAN
57 MINI CARD -WiFi/WMAX
58-59 Reserve
60 SATA(HDD & CD_ROM)
61-62 USB (Jacks & Camera & BT & FP con & eSATA)
63-64 DC-IN / Discharge / NVM Reserved
5 5
65-66 CIR, LID, MDC, SW, LED, Power BTN, Debug Other int CONNs
67-68 LAN / RJ45 / RJ11 Title : PAGE INDEX
BU1-RD Div.1-HW RD Dept.1 Engineer: Elmer Chiu
Size Project Name Rev
Custom
BIC50 2.0
Date: Tuesday, May 03, 2011 Sheet 3 of 77
A B C D E
5 4 3 2 1
U0701E
RSVD32 AJ13
RSVD33 AJ12
U0701A AP25
PEG_COMP 2 R0701 RSVD1
PEG_ICOMPI B26 1 49.9Ohm 1% AL25 RSVD2 RSVD34 AH25
PEG_ICOMPO A26 AL24 RSVD3 RSVD35 AK26
D 14 DMI_TXN0 A24 DMI_RX#[0] PEG_RCOMPO B27 M_VREFDQ_CHA/B AL22 RSVD4 D
14 DMI_TXN1 C23 A25 EXP_RBIAS 2 R0702 1 750Ohm 1% AJ33 AL26
B22
DMI_RX#[1] PEG_RBIAS for CFD only AG9
RSVD5 RSVD36
AR2
14 DMI_TXN2 DMI_RX#[2] RSVD6 RSVD_NCTF_37
14 DMI_TXN3 A21 DMI_RX#[3] PEG_RX#[0] K35 M27 RSVD7
PEG_RX#[1] J34 L28 RSVD8 RSVD38 AJ26
14 DMI_TXP0 B24 J33 T0723 1 VREFDQ_CHA J17 AJ27
DMI_RX[0] PEG_RX#[2] T0721 VREFDQ_CHB RSVD9 RSVD39
14 DMI_TXP1 D23 DMI_RX[1] PEG_RX#[3] G35 1 H17 RSVD10
DMI
DMI
14 DMI_TXP2 B23 DMI_RX[2] PEG_RX#[4] G32 G25 RSVD11
14 DMI_TXP3 A22 DMI_RX[3] PEG_RX#[5] F34 G17 RSVD12
PEG_RX#[6] F31 E31 RSVD13 RSVD_NCTF_40 AP1 H_RSVD40 1 T0725
14 DMI_RXN0 D24 DMI_TX#[0] PEG_RX#[7] D35 E30 RSVD14 RSVD_NCTF_41 AT2 H_RSVD41 1 T0726
14 DMI_RXN1 G24 DMI_TX#[1] PEG_RX#[8] E33
14 DMI_RXN2 F23 DMI_TX#[2] PEG_RX#[9] C33 RSVD_NCTF_42 AT3 H_RSVD42 1 T0727
14 DMI_RXN3 H23 DMI_TX#[3] PEG_RX#[10] D32 RSVD_NCTF_43 AR1 H_RSVD43 1 T0728
PEG_RX#[11] B32
14 DMI_RXP0 D25 DMI_TX[0] PEG_RX#[12] C31
14 DMI_RXP1 F24 DMI_TX[1] PEG_RX#[13] B28
14 DMI_RXP2 E23 DMI_TX[2] PEG_RX#[14] B30 RSVD45 AL28
G23 A31 H_CFG0 AM30 AL29
14 DMI_RXP3 DMI_TX[3] PEG_RX#[15] CFG[0] RSVD46
T0701 1H_CFG1 AM28 AP30
T0702 CFG[1] RSVD47
PEG_RX[0] J35 1H_CFG2 AP31 CFG[2] RSVD48 AP32
H34 H_CFG3 AL32 AL27
PEG_RX[1] H_CFG4 CFG[3] RSVD49
PEG_RX[2] H33 AL30 CFG[4] RSVD50 AT31
E22 F35 T0705 1H_CFG5 AM31 AT32
14 FDI_TXN0 FDI_TX#[0] PEG_RX[3] CFG[5] RSVD51
D21 G33 T0706 1H_CFG6 AN29 AP33
14 FDI_TXN1 FDI_TX#[1] PEG_RX[4] CFG[6] RSVD52
D19 E34 T0707 1H_CFG7 AM32 AR33
14 FDI_TXN2 FDI_TX#[2] PEG_RX[5] CFG[7] RSVD53
D18 F32 T0708 1H_CFG8 AK32 AT33
14 FDI_TXN3 FDI_TX#[3] PEG_RX[6] CFG[8] RSVD_NCTF_54
RESERVED
G21 D34 T0709 1H_CFG9 AK31 AT34
14 FDI_TXN4
PCI EXPRESS -- GRAPHICS
FDI_TX#[4] PEG_RX[7] T0710 CFG[9] RSVD_NCTF_55
14 FDI_TXN5 E19 FDI_TX#[5] PEG_RX[8] F33 1H_CFG10 AK28 CFG[10] RSVD_NCTF_56 AP35
C F21 B33 T0711 1H_CFG11 AJ28 AR35 C
14 FDI_TXN6 FDI_TX#[6] PEG_RX[9] CFG[11] RSVD_NCTF_57
Intel(R) FDI
Intel(R) FDI
G18 D31 T0712 1H_CFG12 AN30 AR32
14 FDI_TXN7 FDI_TX#[7] PEG_RX[10] CFG[12] RSVD58
A32 T0713 1H_CFG13 AN32
PEG_RX[11] T0714 CFG[13]
PEG_RX[12] C30 1H_CFG14 AJ32 CFG[14]
D22 A28 T0715 1H_CFG15 AJ29 E15
14 FDI_TXP0 FDI_TX[0] PEG_RX[13] CFG[15] RSVD_TP_59
C21 B29 T0716 1H_CFG16 AJ30 F15
14 FDI_TXP1 FDI_TX[1] PEG_RX[14] CFG[16] RSVD_TP_60
D20 A30 T0717 1H_CFG17 AK30 A2
14 FDI_TXP2 FDI_TX[2] PEG_RX[15] CFG[17] KEY
C18 T0718 1H_CFG18 H16 D15
14 FDI_TXP3 FDI_TX[3] RSVD_TP_86 RSVD62
14 FDI_TXP4 G22 FDI_TX[4] PEG_TX#[0] L33 RSVD63 C15
E20 M35 AJ15 H_RSVD64 1 T0722
14 FDI_TXP5 FDI_TX[5] PEG_TX#[1] RSVD64
F20 M33 Place Near CON7501 AH15 H_RSVD65 1 T0724
14 FDI_TXP6 FDI_TX[6] PEG_TX#[2] RSVD65
14 FDI_TXP7 G19 FDI_TX[7] PEG_TX#[3] M30
PEG_TX#[4] L31 B19 RSVD15
14 FDI_FSYNC0 F17 FDI_FSYNC[0] PEG_TX#[5] K32 A19 RSVD16
14 FDI_FSYNC1 E17 FDI_FSYNC[1] PEG_TX#[6] M29
J31 T0719 1 H_RSVD17 A20
PEG_TX#[7] T0720 H_RSVD18 RSVD17
14 FDI_INT C17 FDI_INT PEG_TX#[8] K29 1 B20 RSVD18
PEG_TX#[9] H30 RSVD_TP_66 AA5
14 FDI_LSYNC0 F18 FDI_LSYNC[0] PEG_TX#[10] H29 U9 RSVD19 RSVD_TP_67 AA4
14 FDI_LSYNC1 D17 FDI_LSYNC[1] PEG_TX#[11] F29 T9 RSVD20 RSVD_TP_68 R8
PEG_TX#[12] E28 RSVD_TP_69 AD3
PEG_TX#[13] D29 AC9 RSVD21 RSVD_TP_70 AD2
PEG_TX#[14] D27 AB9 RSVD22 RSVD_TP_71 AA2
PEG_TX#[15] C26 RSVD_TP_72 AA1
RSVD_TP_73 R9
PEG_TX[0] L34 RSVD_TP_74 AG7
PEG_TX[1] M34 C1 RSVD_NCTF_23 RSVD_TP_75 AE3
PEG_TX[2] M32 A3 RSVD_NCTF_24
1KOhm 1 R0715 2 FDI_FSYNC0 L30
B DSC PEG_TX[3] B
PEG_TX[4] M31 RSVD_TP_76 V4
1KOhm 1 R0711 2 FDI_FSYNC1 K31 V5
DSC PEG_TX[5] RSVD_TP_77
PEG_TX[6] M28 RSVD_TP_78 N2
1KOhm 1 R0713 2 FDI_INT H31 J29 AD5
DSC PEG_TX[7] RSVD26 RSVD_TP_79
PEG_TX[8] K28 J28 RSVD27 RSVD_TP_80 AD7
1KOhm 1 R0712 2 FDI_LSYNC0 G30 W3
DSC PEG_TX[9] RSVD_TP_81
PEG_TX[10] G29 A34 RSVD_NCTF_28 RSVD_TP_82 W2
1KOhm 1 R0714 2 FDI_LSYNC1 F28 A33 N3
DSC PEG_TX[11] RSVD_NCTF_29 RSVD_TP_83
PEG_TX[12] E27 RSVD_TP_84 AE5
PEG_TX[13] D28 C35 RSVD_NCTF_30 RSVD_TP_85 AD9
PEG_TX[14] C27 B35 RSVD_NCTF_31
PEG_TX[15] C25
VSS AP34 H_RSVD86
Default: DSC Only VSS (AP34):
SOCKET989
DSC only: Pop all resisters NC CRB
UMA only: Depop all resisters SOCKET989 EDS/DG GND
H_CFG0
H_CFG3 H_CFG4
1
CFG0 : PCIE Config Strap CFG3 : PCIE Lane Reversal CFG4 : eDP Presence
1
1
R0708
3.01KOHM R0709 R0710
@ 1% H = Single PEG (Default) 3.01KOHM H = Normal Operation (Default) 3.01KOHM H = Disable (Default)
1% @ 1%
L = Bifurcation enabled L = Lane Numbers Reversed L = Enable
2
A A
DSC
2
2
Title : CPU(1)
BU1-RD Div.1-HW RD Dept.1 Engineer: Elmer Chiu
Size Project Name Rev
Custom
BIC50 2.0
Date: Tuesday, May 03, 2011 Sheet 7 of 77
5 4 3 2 1
5 4 3 2 1
U0701D
U0701C
22 M_B_DQ[0:63] SB_CK[0] W8 M_CLK_DDR2 22
SB_CK#[0] W9 M_CLK_DDR#2 22
AA6 M_B_DQ0 B5 M3
SA_CK[0] M_CLK_DDR0 21 SB_DQ[0] SB_CKE[0] M_CKE2 22
AA7 M_B_DQ1 A5
21 M_A_DQ[0:63] SA_CK#[0] M_CLK_DDR#0 21 SB_DQ[1]
P7 M_B_DQ2 C3
SA_CKE[0] M_CKE0 21 SB_DQ[2]
D M_A_DQ0 A10 M_B_DQ3 B3 V7 D
SA_DQ[0] SB_DQ[3] SB_CK[1] M_CLK_DDR3 22
M_A_DQ1 C10 M_B_DQ4 E4 V6
SA_DQ[1] SB_DQ[4] SB_CK#[1] M_CLK_DDR#3 22
M_A_DQ2 C7 M_B_DQ5 A6 M2
SA_DQ[2] SB_DQ[5] SB_CKE[1] M_CKE3 22
M_A_DQ3 A7 Y6 M_B_DQ6 A4
SA_DQ[3] SA_CK[1] M_CLK_DDR1 21 SB_DQ[6]
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