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5 4 3 2 1
AAB70 AMD Brazos Platform Rev. 2.0
D
BLOCK DIAGRAM R 1.1 /0301
D
laud SDVL
LCD Panel Travis DP to LVDS
ANX3110
Page 45 AMD FUSION APU
Page 45
HDMI CON
SDMT
SDMT
SDMT
SDMT DDR3 DDR3 SO-DIMM X 2
Page 48 Zacate Page 7, 8
TRC
TRC
TRC
TRC
CRT CON
Page 46 Page 3 ~ 6
UMI X 4
Seymour XT/M2 PCI-E x 4
C C
Page 70~79 Power
EICP 1
LAN 10/100M RJ45
CPU_VCORE
AR8158 Page 80
Page 34
Page 33
System
Debug Conn. EICP
E MiniCard Page 81
Page 44
TP On/Off button AMD BSU
BSU
BSU
BSU WLAN +1.0VS
Shirley Peak/ Echo Peak Page 82
CPL
CPL
CPL
CPL Page 53
Touchpad EC
Keyboard
NPCE791 / 795 FCH DDR & VTT
Page 83
Page 31 Page 30
SPI ROM s
s
u
u
HUDSON-M1 +1.8VS
B
B Page 84
Page 28 M
M
S
S
B +VDDC_VGA B
0.2BSU 1 Page 87
Thermal Sensor USB Port(2)
Page 52
PWM Fan Charger
Page 50 0 Page 88
Page 20 ~ 28
USB Port(1)
Page 52 Detect
Page 90
Int Mic A
T 8
Page 45 Azalia Codec ailazA
ailazA
ailazA
ailazA A CMOS Camera Load Switch
S
ALC271 Page 45 Page 91
HP & SPK CON
Page 36,38 1 CardReader
Page 37 ODD 7 Power Protect
Page 51 RTS5138 Page 92
Page 40
0
HDD
Page 51
A A
Discharge Circuit DC & BATT.Conn ODD Board TP_Button
Page 57 Page 57 Page 58 Page 60
Reset Circuit Skew Holes Power Switch I/O Board
Page 32 Page 65 Page 59 Page 65 Title : BLOCK DIAGRAM
Engineer: Allen_CD_Wu
Size Project Name Rev
Custom AAB70 1.1
Date: Thursday, April 21, 2011 Sheet 1 of 99
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title : System Setting
Engineer: Allen_CD_Wu
Size Project Name Rev
C AAB70 1.1
Date: Monday, March 21, 2011 Sheet 2 of 99
5 4 3 2 1
5 4 3 2 1
M_A_DQ[63:0] 7,8
U0301E
7,8 M_A_A[15:0]
M_A_A0 R17 B14 M_A_DQ0
M_A_A1 M_ADD[0] ONTARIO (2.0) M_DATA[0] M_A_DQ1
H19 A15
M_A_A2 M_ADD[1] PART 1 OF 5 M_DATA[1] M_A_DQ2
J17 A17
M_A_A3 M_ADD[2] M_DATA[2] M_A_DQ3
H18 D18
M_A_A4 M_ADD[3] M_DATA[3] M_A_DQ4
H17 A14
M_A_A5 M_ADD[4] M_DATA[4] M_A_DQ5
G17 C14
M_A_A6 M_ADD[5] M_DATA[5] M_A_DQ6
H15 C16
M_A_A7 M_ADD[6] M_DATA[6] M_A_DQ7
G18 D16
M_A_A8 M_ADD[7] M_DATA[7]
F19
D
M_A_A9 M_ADD[8] M_A_DQ8 D
E19 C18
M_A_A10 M_ADD[9] M_DATA[8] M_A_DQ9
T19 A19
M_A_A11 M_ADD[10] M_DATA[9] M_A_DQ10
F17 B21
M_A_A12 M_ADD[11] M_DATA[10] M_A_DQ11
E18 D20
M_A_A13 M_ADD[12] M_DATA[11] M_A_DQ12 /DSC
W17 A18 U0301A
M_A_A14 M_ADD[13] M_DATA[12] M_A_DQ13 PCIEG_TXP0_C C0302
E16 B18 70 PCIEG_RXP0 AA6 AB6 1 /DSC2 0.1UF/10V PCIEG_TXP0 70
M_A_A15 M_ADD[14] M_DATA[13] M_A_DQ14 P_GPP_RXP[0] P_GPP_TXP[0] PCIEG_TXN0_C C0304 0.1UF/10V
G15 A21 70 PCIEG_RXN0 Y6 AC6 1 2 PCIEG_TXN0 70
M_ADD[15] M_DATA[14] M_A_DQ15 P_GPP_RXN[0] ONTARIO (2.0) P_GPP_TXN[0] /DSC
C20
M_DATA[15] PART 2 OF 5 PCIEG_TXP1_C C0307
7,8 M_A_BS0 R18 70 PCIEG_RXP1 AB4 AB3 1 /DSC2 0.1UF/10V PCIEG_TXP1 70
M_BANK[0] M_A_DQ16 P_GPP_RXP[1] P_GPP_TXP[1] PCIEG_TXN1_C C0309 0.1UF/10V
7,8 M_A_BS1 T18 C23 70 PCIEG_RXN1 AC4 AC3 1 2 PCIEG_TXN1 70
M_BANK[1] M_DATA[16] M_A_DQ17 P_GPP_RXN[1] P_GPP_TXN[1] /DSC
7,8 M_A_BS2 F16 D23
M_BANK[2] M_DATA[17] M_A_DQ18 PCIEG_TXP2_C C0311
7,8 M_A_DM[7:0] F23 70 PCIEG_RXP2 AA1 Y1 1 /DSC2 0.1UF/10V PCIEG_TXP2 70
M_A_DM0 M_DATA[18] M_A_DQ19 P_GPP_RXP[2] P_GPP_TXP[2] PCIEG_TXN2_C C0312 0.1UF/10V
D15 F22 70 PCIEG_RXN2 AA2 Y2 1 2 PCIEG_TXN2 70
M_A_DM1 M_DM[0] M_DATA[19] M_A_DQ20 P_GPP_RXN[2] P_GPP_TXN[2] /DSC
B19 C22
PCIE I/F
M_A_DM2 M_DM[1] M_DATA[20] M_A_DQ21 PCIEG_TXP3_C C0314
D21 D22 70 PCIEG_RXP3 Y4 V3 1 /DSC2 0.1UF/10V PCIEG_TXP3 70
M_A_DM3 M_DM[2] M_DATA[21] M_A_DQ22 P_GPP_RXP[3] P_GPP_TXP[3] PCIEG_TXN3_C C0316 0.1UF/10V
H22 F20 70 PCIEG_RXN3 Y3 V4 1 2 PCIEG_TXN3 70
M_A_DM4 M_DM[3] M_DATA[22] M_A_DQ23 P_GPP_RXN[3] P_GPP_TXN[3]
P23 F21
M_A_DM5 M_DM[4] M_DATA[23] R0315
V23 +1.0VS 1 /DSC 2 2KOhm P_ZVDD_10 Y14 AA14 P_ZVSS R0318 1 /DSC 2 1.27KOhm
M_A_DM6 M_DM[5] M_A_DQ24 P_ZVDD_10 P_ZVSS
AB20 H21
M_A_DM7 M_DM[6] M_DATA[24] M_A_DQ25
AA16 H23
M_DM[7] M_DATA[25] M_A_DQ26
K22
M_A_DQS0 M_DATA[26] M_A_DQ27 UMI_TXP0_C C0301
A16 K21 20 UMI_RXP0 AA12 AB12 1 2 0.1UF/10V UMI_TXP0 20
M_A_DQS#0 M_DQS_H[0] M_DATA[27] M_A_DQ28 P_UMI_RXP[0] P_UMI_TXP[0] UMI_TXN0_C C0303
B16 G23 20 UMI_RXN0 Y12 AC12 1 2 0.1UF/10V UMI_TXN0 20
M_A_DQS1 M_DQS_L[0] M_DATA[28] M_A_DQ29 P_UMI_RXN[0] P_UMI_TXN[0]
B20 H20
M_A_DQS#1 M_DQS_H[1] M_DATA[29] M_A_DQ30 UMI_TXP1_C C0305
A20 K20 20 UMI_RXP1 AA10 AC11 1 2 0.1UF/10V UMI_TXP1 20
M_A_DQS2 M_DQS_L[1] M_DATA[30] M_A_DQ31 P_UMI_RXP[1] P_UMI_TXP[1] UMI_TXN1_C C0306
E23 K23 20 UMI_RXN1 Y10 AB11 1 2 0.1UF/10V UMI_TXN1 20
M_DQS_H[2] M_DATA[31] P_UMI_RXN[1] P_UMI_TXN[1]
UMI I/F
M_A_DQS#2 E22
7,8 M_A_DQS[7:0] M_DQS_L[2]
M_A_DQS3 J22 N23 M_A_DQ32 AB10 AA8 UMI_TXP2_C C0308 1 2 0.1UF/10V
MEMORY I/F
M_DQS_H[3] M_DATA[32] 20 UMI_RXP2 P_UMI_RXP[2] P_UMI_TXP[2] UMI_TXP2 20
M_A_DQS#3 J23 P21 M_A_DQ33 20 UMI_RXN2 AC10 Y8 UMI_TXN2_C C0310 1 2 0.1UF/10V UMI_TXN2 20
7,8 M_A_DQS#[7:0] M_DQS_L[3] M_DATA[33] P_UMI_RXN[2] P_UMI_TXN[2]
M_A_DQS4 R22 T20 M_A_DQ34
M_A_DQS#4 M_DQS_H[4] M_DATA[34] M_A_DQ35 UMI_TXP3_C C0313
P22 T23 20 UMI_RXP3 AC7 AB8 1 2 0.1UF/10V UMI_TXP3 20
M_A_DQS5 M_DQS_L[4] M_DATA[35] M_A_DQ36 P_UMI_RXP[3] P_UMI_TXP[3] UMI_TXN3_C C0315
W22 M20 20 UMI_RXN3 AB7 AC8 1 2 0.1UF/10V UMI_TXN3 20
M_A_DQS#5 M_DQS_H[5] M_DATA[36] M_A_DQ37 P_UMI_RXN[3] P_UMI_TXN[3]
V22 P20
M_A_DQS6 M_DQS_L[5] M_DATA[37] M_A_DQ38 BGA413_FT1
AC20 R23
M_A_DQS#6 M_DQS_H[6] M_DATA[38] M_A_DQ39
AC21 T22
+1.5V M_A_DQS7 M_DQS_L[6] M_DATA[39]
AB16
M_A_DQS#7 M_DQS_H[7] M_A_DQ40
AC16 V20
M_DQS_L[7] M_DATA[40] M_A_DQ41
C V21 C
M_DATA[41] M_A_DQ42
7 M_CLK_DDR0 M17 Y23
M_CLK_H[0] M_DATA[42]
1
M16 Y22 M_A_DQ43
7 M_CLK_DDR#0 M_CLK_L[0] M_DATA[43]
M19 T21 M_A_DQ44
7 M_CLK_DDR1 M_CLK_H[1] M_DATA[44]
R0301 M18 U23 M_A_DQ45
7 M_CLK_DDR#1 M_CLK_L[1] M_DATA[45]
1KOhm N18 W23 M_A_DQ46
8 M_CLK_DDR2 M_CLK_H[2] M_DATA[46]
N19 Y21 M_A_DQ47
8 M_CLK_DDR#2
2
M_CLK_L[2] M_DATA[47]
8 M_CLK_DDR3 L18
M_CLK_H[3]
8 M_CLK_DDR#3 L17 Y20 M_A_DQ48
M_CLK_L[3] M_DATA[48]
AB22 M_A_DQ49
M_DATA[49]
7,8 M_DRAMRST# L23 AC19 M_A_DQ50
M_RESET_L M_DATA[50]
7,8 PM_EXTTS#0 N17 AA18 M_A_DQ51
M_EVENT_L M_DATA[51]
AA23 M_A_DQ52
M_DATA[52]
AA20 M_A_DQ53
M_DATA[53]
7,8 M_CKE0 F15 AB19 M_A_DQ54
M_CKE[0] M_DATA[54]
7,8 M_CKE1 E15 Y18 M_A_DQ55
M_CKE[1] M_DATA[55]
AC17 M_A_DQ56
M_DATA[56]
Y16 M_A_DQ57
M_DATA[57]
7 M_ODT0 W19 AB14 M_A_DQ58
M0_ODT[0] M_DATA[58]
7 M_ODT1 V15 AC14 M_A_DQ59
M0_ODT[1] M_DATA[59]
8 M_ODT2 U19 AC18 M_A_DQ60
M1_ODT[0] M_DATA[60]
8 M_ODT3 W15 AB18 M_A_DQ61
M1_ODT[1] M_DATA[61] +1.5V
AB15 M_A_DQ62
M_DATA[62]
7 M_CS#0 T17 AC15 M_A_DQ63
M0_CS_L[0] M_DATA[63]
7 M_CS#1 W16
M0_CS_L[1]
8 M_CS#2 U17
M1_CS_L[0] M_VREF
8 M_CS#3 V16 M23
M1_CS_L[1] M_VREF
7,8 M_A_RAS# U18
M_RAS_L
7,8 M_A_CAS# V19
M_CAS_L M_ZVDDIO_MEM_S R0302 39.2Ohm
7,8 M_A_WE# V17 M22 2 1
M_WE_L M_ZVDDIO_MEM_S
10V320000037
BGA413_FT1
0102-00F20PB
nb_bga_413p_31_748x748
B B
1228
M_CKE0
+1.5V
M_CKE1
2
R0305
2
2
1KOhm
R0307 R0308
68Ohm 68Ohm
1
M_VREF
1
1
1
1
1
C0317 C0318
R0306
1KOhm
2
2
0.1UF/10V 1000PF/50V
2
place within 1000mils with APU
A A
Title : CPU(1)_DMI,PEG
BG1/HW2 Engineer: Allen_CD_Wu
Size Project Name Rev
C AAB70 1.1
Date: Thursday, April 21, 2011 Sheet 3 of 99
5 4 3 2 1
5 4 3 2 1
U0301B Allen
ANALOG/DISPLAY/MISC R1.1
48 HDMI_TX2P_APU A8 H3 DP_ZVSS R0413 1 2 133Ohm
TDP1_TXP[0] DP_ZVSS CRT_R_GND
48 HDMI_TX2N_APU B8 TDP1_TXN[0]
G2 CRT_G_GND
DP MISC
DP_BLON LCD_BACKEN 45
48 HDMI_TX1P_APU B9 H2 CRT_B_GND
TDP1_TXP[1] DP_DIGON L_VDDEN 45
48 HDMI_TX1N_APU A9 H1
DISPLAYPORT 1
TDP1_TXN[1] DP_VARY_BL L_BKLT_CTRL 45
D10
0930
48 HDMI_TX0P_APU TDP1_TXP[2]
D 48 HDMI_◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo