Service Manuals, User Guides, Schematic Diagrams or docs for : apple Apple IMAC G5_MLB_PB15_051-6338_RevC
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8 7 6 5 4 3 2 1
DRAWING CK ENG
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD APPD
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. REV ZONE ECN DESCRIPTION OF CHANGE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. DATE DATE
02 248015 ENGINEERING RELEASED 12/05/02 ?
D PAGE CONTENTS PAGE CONTENTS D
VIDEO CONNECTORS - INVERTER, DVI, S-VIDEO,
22
1
2
TITLE PAGE AND CONTENTS
SYSTEM BLOCK DIAGRAM 23
LVDS
KBD,TPAD,HALL EFFECT,PWR BUTTON,LMU/SENSOR
SCHEM,MLB,PB15 Fri Jan 23 20:30:40 2004
INTERNAL CONNECTORS - AIRPORT, HARD DRIVE,
3 POWER BLOCK DIAGRAM 24 OPTICAL DRIVE
4 PCB NOTES AND HOLES 25 FAN CONTROLLER, USB MODEM/SOFT MODEM,
SOUND/LEFT USB/BLUETOOTH, SERIAL DEBUG
5 MPC7447 MAXBUS INTERFACE 26 GIGABIT ETHERNET INTERFACE
BOM OPTIONS (IN COMMON PARTS)
6 MPC7447 DATA / NC PINS / BOOTBANGER 27 FIREWIRE PHY STUFF NO STUFF
1_8V_MAXBUS 1_5V_MAXBUS
7 CPU PLL AND CONFIGURATION STRAPS 28 FIREWIRE PORTS
SSCG NO_SSCG
C 8 INTREPID MAXBUS AND BOOT STRAPS 29 PMU 5V_HD_LOGIC 3V_HD_LOGIC
C
NO_BBANG BBANG
9 INTREPID MEMORY INTERFACE / BOOT ROM 30 BATTERY CHARGER AND CONNECTOR
INT_2_5V_COLD INT_2_5V_HOT
10 DDR MEMORY MUXES 31 PBUS SUPPLY / PMU SUPPLY / BACKUP BATTERY ATI_MEMIO_HI ATI_MEMIO_LO
USB_MODEM SOFT_MODEM
11 400PIN STACKED DDR SODIMM CONNECTOR 32 3.3V / 5V SYSTEM POWER SUPPLY
GPU_PWRMSR INT_TMDS
12 INTREPID AGP 4X/PCI 33 CPU CORE VOLTAGE POWER SUPPLY
GPU_SS
13 INTREPID ENET/FW/UATA/EIDE INTERFACES 34 1.5V/ 1.8V / 2.5V SYSTEM POWER SUPPLIES VGA_BUFFER_RES
EXT_TMDS
14 INTREPID GPIOS/SERIAL/USB INTERFACES/SSCG 35 SIGNAL CONSTRAINTS (1 OF 4) - DDR MEM/CLK
15 INTREPID POWER RAILS/1.5V LDO 36 SIGNAL CONSTRAINTS (2 OF 4) - CPU
B 16 INTREPID DECOUPLING 37 SIGNAL CONSTRAINTS (3 OF 4) - DIGITAL/DIFF B
17 USB 2.0 INTERFACE (uPD720101) 38 SIGNAL CONSTRAINTS (4 OF 4) - POWER NETS
18 CARDBUS INTERFACE (PCI1510) 39 FUNCTIONAL TESTPOINTS
M10 AGP INTERFACE & SPREAD SPECTRUM SUPPORT
19 External TMDS (DVI Transmitter SIL1162) 40 REVISION HISTORY
20 M10 LVDS/TMDS/GPIO & GPU VCORE 41 SIGNAL LOCATIONS
21 M10 POWER 42 COMPONENT LOCATIONS (1 OF 2)
43 COMPONENT LOCATIONS (2 OF 2)
DIMENSIONS ARE IN MILLIMETERS
METRIC Apple Computer Inc.
XX
A TABLE_5_HEAD
X.XX
DRAFTER DESIGN CK NOTICE OF PROPRIETARY PROPERTY A
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
X.XXX PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
TABLE_5_ITEM AGREES TO THE FOLLOWING
051-6338 1 SCHEM,MLB,PB15 SCH1 ENG APPD MFG APPD
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
TABLE_5_ITEM ANGLES II NOT TO REPRODUCE OR COPY IT
820-1441 1 PCBF,MLB,PB15 PCB1 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
TABLE_5_ITEM QA APPD DESIGNER TITLE
065-3951 1 CMNPRTS,MLB,PB15 DMS1 DMS630-4285&DMS630-4721 DO NOT SCALE DRAWING
065-3952
065-4479
1
1
SELPRTS,MLB,PB15,BTR
SELPRTS,MLB,PB15,BST
DMS2
DMS3
DMS630-4285
DMS630-4721
TABLE_5_ITEM
TABLE_5_ITEM
RELEASE SCALE
NONE
SCHEM,MLB,PB15"
SIZE DRAWING NUMBER REV.
MATERIAL/FINISH
NOTED AS D 051-6338 C
THIRD ANGLE PROJECTION APPLICABLE SHT 1 OF 40
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
J24 J20 J2
J23
RUX Board
Ethernet FW - A FW - B
Connector Connector
Connector Connector P.23
P.26 P.28 P.28 J19
J26 J27
LMU LUX Board
2 DATA PAIRS Connector Battery Power Supply DC-In
@ 200MHz 2 DATA PAIRS
4 DATA PAIRS @ 400MHZ P.23 Connector & Charger Connector
U36 D
D U43 J13 P.30 P.30-34 P.30
FireWire OPTICAL DRIVE
Ethernet PHY J3 J8
PHY Connector SLEEP
P.27 LIO/Audio SMBUS
P.26 P.24 LED
Connector 3.3V
G/MII J12
P.25 P.23
3.3V 1394 OHCI ULTRA ATA/100 U28
10/100/1000 3.3V Connector
8BIT TX 8BIT TX/RX
50MHZ P.24
EIDE
I2S I2C
U53/J1/J18
Fan
PMU
8BIT RX
125MHZ I2C Circuit P.29 J5
UIDE P.25 SERIAL
CARDBUS
5V
NOT USED J10 J11 Connector
ETHERNET FIREWIRE TRACKPAD Keyboard P.18
UATA 100 EIDE CARDSLOT I2S I2C
10/100/1000 400 MB/S P.13 Connector Connector
P.13 P.13 P.13 P.14 J28
P.13 P.13 P.14 P.23 P.23 33MHZ
C USB PORT A SCCA
Serial Debug 16/32 BITS C
NOT USED Connector 3.3V/5V
P.14 P.14
P.25 U8
NOT USED USB PORT B
P.14
USB PORT C
U51 VIA/PMU
P.14 U11 J6
TI PCI1510
CardBus
NOT USED P.14
J3
BlueTooth (LIO) NOT USED USB PORT D
INTREPID BOOTROM
P.12
BOOT ROM
1M X 8
AIRPORT
Connector
Controller
P.18
P.14 P.9 P.24
P.25
USB PORT E PCI
J15 P.14 64BITS PCI BUS
33MHZ 32BITS
Modem/SW Modem USB PORT F 33MHZ
P.14 P.12
Connector AGP BUS 3.3V
1.5V/3.3V U47
P.25
32BITS MEMORY MEMORY
B
MAXBUS
P.8 4X AGP
66MHZ ATI CH. A CH. C
U17
B
INTREPID NEC USB2.0
I2C MAXBUS
1.8V
DDR MEMORY
P.9
P.12
M10 (INTERNAL MEM) (INTERNAL MEM)
MEMORY MEMORY
EHCI HC
167MHZ
32BIT ADDRESS MEMORY BUS
64MB CH. B CH. D
P.17
J3
64BIT DATA 2.5V P.19-21 (INTERNAL MEM) (INTERNAL MEM)
167MHZ J4 LEFT USB
64BITS (VIA LIO)
U56 U16/U18/U28/U27
(VIA SIL1162)
COMPOSITE
Inverter P.25
EDID (I2C)
S-VIDEO
CPU PLL Connector
TMDS
2:1 DDR MUXES
APOLLO Config P.22
J17
LVDS
RIGHT USB
RGB
DDC
P.10
CPU P.7
J14 J21 J22
(VIA STATLER)
P.25
(MPC7447) PMU
P.5-6 LCD Panel S-Video DVI-I
J25 Connector Connector Connector
DDR SDRAM DIMM 0 P.22 P.22 P.22 SYSTEM BLOCK DIAGRAM
A NOTICE OF PROPRIETARY PROPERTY
A
DDR SDRAM DIMM 1 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
SO-DIMM Connector I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
P.11 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6338 C
SCALE SHT OF
NONE 2 40
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
POWER SYSTEM ARCHITECTURE
+5V_MAIN
1V20_REF -
PG 31
BACKLIGHT MAP31 DDR CORE DCDC_EN
>~13.44V TURNS-ON
+ VCC
<~13.44V SHUTS-OFF MAP31 DDR I/O SLEEP
INVERTER MAIN 2.5V/1.5V
RUN/SS DDR POWER D
D AC DC/DC
INRUSH BUCK +2.5V_MAIN MAXBUS
ADAPTER
+PBUS
LIMITER +24V_PBUS REGULATOR (MAX1715) SEQUENCING
VCC
IN PG 30
+PBUS PG 34 PGOOD 1_5V_2_5V_OK
(LTC1625)
PG 30 PG 31 SHUTDOWN: STOPPED
14V_PBUS +5V_MAIN SLEEP: RUNNING +1.5V_MAIN
AC: 12.8V RUN: RUNNING
NO AC: BATTERY VOLTAGE INTREPID CORE
1625 NOT RUNNING TURNS ON OUTPUT @ 2.4V AGP I/O +5V_MAIN
ON1/ON2
SHUTDOWN: RUNNING
SLEEP: RUNNING VCC SHDN
RUN: RUNNING
+5V_MAIN
DCDC_EN_L
AFTER PMU IS UP AND RUNNING
DCDC_EN_L WILL PULL ON1/ON2
DC/DC
RC AT 1M*0.047UF @ 24V (MAX1717)
+3V_PMU STARTS 2.0MSEC AFTER DCDC_EN_L BECOMES LOW
LOW IN SHUTDOWN
+5V_MAIN
+BATT LDO +3V_PMU SHUTDOWN: STOPPED
RUN/SS - 5V
TURNS ON AT >1V +5V_MAIN +PBUS EXT_VCC SLEEP: STOPPED
+4_6V_BU VCC RUN: RUNNING C
C PG 31
<100UA ALLOWED
INTERNAL ZENER CLAMP TO 6V DC/DC
MAIN 3V/5V PGOOD 3V_5V_OK GPU_VCORE PG 33
(LTC1778)
DC/DC SHUTDOWN: STOPPED +1.2V
(LTC3707) HOLDS BOTH RUN/SS AT GND
DCDC_EN SLEEP: D3COLD CPU_VCORE
VCC
WHEN IT'S CONNECTED TO GND
RUN: RUNNING (+1.385V)
14V_PBUS PG 32 STBYMD TURNS CONTROL TO RUN/SS
WHEN IT'S OPEN
SLEEP
D3_COLD TURNS ON AS LOW AS 0.8V/TYP 1.5V
INTERNAL 1.2UA CURRENT SOURCE
SHUTDOWN: STOPPED
SLEEP: RUNNING GPU_VCORE RUN/SS PG 20
1_5V_2_5V_OK WILL NOT PULL LOW UNTIL
RUN: RUNNING SEQUENCING
BACKUP 14V CHARGES BACKUP BATTERY
INTERNAL ZENER CLAMP TO 6V
+3.3V_MAIN
+5V_MAIN TURNS ON
HOWEVER, 5V SHOULD TURN ON ~2.23MS AFTER
<100UA ALLOWED 1M & 0.1UF @14V, IT TAKES DCDC_EN_L OR PMU_POWERUP_L
BATTERY TURNS ON AT >1V
RUN/SS - 3V
~5.88MS TO START SWITCHER 1_5V_2_5V_OK
D3_HOT
BECOMES '1'; MUCH LESS THAN THE
RC CHARGING AT INT_VCC (5V)
DCDC_EN_L
D3_HOT
24V IS OUTPUT ONLY FROM
BACKUP BATTERY
RC AT 1M*0.1UF @ 24V
CHARGER INPUT STARTS ~4.25MSEC AFTER DCDC_EN_L BECOMES LOW
SHUT-DOWN RUN SLEEP RUN SHUT-DOWN
NO INRUSH PROTECTION
& BOOST OUTPUT WHEN ONLY BATTERY IS CONNECTED SLEEP
B PG 31 +24V_PBUS SLEEP_L_LS5 B
BACKUP BATTERY CIRCUIT CHARGES OFF +PBUS
DCDC_EN
AND PREVENTS +PBUS AND +24V_PBUS FROM DROPPING BELOW 6V DC/DC DCDC_EN_L
(UNTIL DRAINED)
(LTC3411) +5V_MAIN ~2.23MS
+1.8V_MAIN
BATTERY +5V_SLEEP
SHUTDOWN: STOPPED MAXBUS +3V_MAIN ~7.36MS
CHARGER SLEEP: STOPPED
RUN: RUNNING +3V_SLEEP
(MAX1772) PG 34 3V_5V_OK 2.4V - ??? MS
PG 30 +2_5V_MAIN ??? MS
+2_5V_SLEEP
+BATT +1_5V_MAIN ??? MS
NO INRUSH PROTECTION +1_5V_SLEEP
3S 2P 18650 CELLS WHEN ONLY BATTERY IS CONNECTED
1_5V_2_5V_OK
(MAX1715 OUTPUT)
BATTERY VOLTAGE 1_5V_2_5V_OK POWER BLOCK DIAGRAM
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