Service Manuals, User Guides, Schematic Diagrams or docs for : apple Apple Powerbook G4 A1025_PBG4_MLB_P88_051-6403_RevE
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CR-1
8 7 6 5 4 3 2 1
CK ENG
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD APPD
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. REV ZONE ECN DESCRIPTION OF CHANGE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. DATE DATE
E 303550 PRODUCTION RELEASED 11/11/03 ?
D PAGE CONTENTS PAGE CONTENTS D
1 TITLE PAGE AND CONTENTS 25 SNAPPER (AUDIO) CONTROL INTERFACE
2 SYSTEM BLOCK DIAGRAM (1 OF 2) 26 HEADPHONE & SPEAKER DRIVERS
3 SYSTEM BLOCK DIAGRAM (2 OF 2) 27 MICROPHONE AMP. / LINE IN AMP
4 POWER BLOCK DIAGRAM 28 GIGABIT ETHERNET INTERFACE
5 PCB NOTES AND HOLES 29 FIREWIRE INTERFACE
6 UNI-N MAXBUS INTERFACE 30 EXTERNAL USB & BT INTERFACES
7 UNI-N MEMORY INTERFACE / SO-DIMM CONNECTOR 31 VIDEO CONNECTORS - LVDS, DVI, S-VIDEO
C 8 UNI-N AGP INTERFACE 32 INTERNAL CONNECTORS - MODEM, DVD, C
CARDSLOT, HARD DRIVE
9 UNI-N PCI INTERFACE 33 PMU INTERFACE CONNECTIONS - KEYBOARD,
TRACKPAD, LEDS, DVI POWER SWITCH
10 UNI-N MISCELLANEOUS INTERFACES 34 PMU INTERFACE
11 UNI-N DECOUPLING 35 DC JACK / BATTERY INTERFACES
12 UNI-N & CPU CONFIGURATION STRAPS 36 PRIMARY STEP-DOWN REGULATOR / CHARGER
13 MPC7455 MAXBUS INTERFACE 37 3.3V / 5V SYSTEM POWER SUPPLY
14 MPC7455 DATA / L3 CACHE INTERFACES 38 1.8V / 2.5V SYSTEM POWER SUPPLIES
15 L3 CACHE 39 CPU CORE VOLTAGE POWER SUPPLY
B 16 KEYLARGO 40 SIGNAL CONSTRAINTS (1 OF 4) B
17 USB 2.0 HOST CONTROLLER INTERFACE
41 SIGNAL CONSTRAINTS (2 OF 4)
18 CARDBUS INTERFACE
42 SIGNAL CONSTRAINTS (3 OF 4)
MOBILITY M7_M9 AGP/MEMORY INTERFACES
19 43 SIGNAL CONSTRAINTS (4 OF 4)
MOBILITY M7_M9 VIDEO/CORE INTERFACES
20 44 REVISION HISTORY (1 OF 2)
21 MOBILITY M7_M9 POWER INTERFACES 45 REVISION HISTORY (2 OF 2)
22 EXTERNAL DDR GRAPHICS RAM
46 SIGNAL LOCATIONS
23 SYSTEM CLOCK GENERATOR & BOOTROM 47 COMPONENT LOCATIONS (1 OF 2)
DIMENSIONS ARE IN MILLIMETERS
XX
METRIC Apple Computer Inc.
A 24 FAN CONTROLLERS 48 COMPONENT LOCATIONS (2 OF 2) X.XX
DRAFTER DESIGN CK NOTICE OF PROPRIETARY PROPERTY A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
X.XXX PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
ENG APPD MFG APPD
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
ANGLES II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
QA APPD DESIGNER TITLE
DO NOT SCALE DRAWING
RELEASE SCALE SCHEM,PBG4,MLB,P88
NONE
SIZE DRAWING NUMBER REV.
MATERIAL/FINISH
NOTED AS D 051-6403 E
THIRD ANGLE PROJECTION APPLICABLE SHT 1 OF 46
8 7 6 5 4 3 2 1
CR-2
8 7 6 5 4 3 2 1
J21 J17 J1 J4
Inverter LCD Panel S-Video DVI-I
Connector Connector Connector Connector
D P.31 P.31 P.31 P.31 D
COMPOSITE
LVDS TMDS
S-VIDEO
J7 J2 J11 J5/J6
FireWire Ethernet EDID (I2C) RGB U2/U7
CardBus USB
Connector Connector (DDC TOO) 16MB DDR Connector Connector
P.29 P.28 U4 SDRAM
MEMORY P.18 P.30
P.22
2 DATA PAIRS
@ 200MHz
4 DATA PAIRS ATI CH. A
(INTERNAL MEM)
U5 U8 Mobility MEMORY VMEM BUS
33MHZ
16/32 BITS Port 3 Port 4
FireWire Ethernet M7_M9 CH. B
2.5V
64BITS
3.3V/5V
PHY PHY P.19-21 183 MHZ U52 U51
P.29 P.28 TI PCI1410A NEC USB 2.0
C G/MII CardBus Host C
3.3V AGP BUS
1394 OHCI 1.5V/3.3V Controller Controller
3.3V 8BIT TX 32BITS P.18 P.17
8BIT RX 66MHZ
8BIT TX/RX
50MHZ 125MHZ
32BITS 32BITS
U9 U53
FIREWIRE ETHERNET 4X AGP PCI PCI BUS Key Largo
400 MB/S 10/100/1000 64BITS 64BITS 32BITS (Expanded
P.10 P.10 P.8 33/66MHZ
P.9 33MHZ View P.3)
UNI-N 1.5 Upper 32 bits
pulled up
3.3V
U23
MEMORY I2C MAXBUS BOOTROM BOOT ROM
P.7 P.10 P.6 P.7 1M X 8
B P.23 B
MEMORY BUS I2C MAXBUS U22
3.3V 1.8V Power Supply
133MHZ 133MHZ U47 & Charger
64BITS 32BIT ADDRESS IMI C5005 I2C
64BIT DATA System Clock PMU P.35-39
P.23 SMBUS
J16 U10 P.34 3.3V Battery
CPU PLL
SDRAM DIMM 0 Fan
Circuit Apollo Config
P.12
SERIAL
5V
P.35
SDRAM DIMM 1 P.24
SO-DIMM Connector
P.7
CPU
(XPC7455)
J28
Trackpad
J14
Keyboard
Connector Connector
P.13-14
P.33 P.33 SYSTEM BLOCK DIAGRAM
A L3 BUS NOTICE OF PROPRIETARY PROPERTY
A
1.5V
200 MHZ THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
18BIT ADDRESS AGREES TO THE FOLLOWING
64BIT DATA I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
U11/U42 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
L3 Cache SIZE DRAWING NUMBER REV.
D 051-6403 E
APPLE COMPUTER INC.
P.15 SCALE SHT OF
NONE 2 46
8 7 6 5 4 3 2 1
CR-3
8 7 6 5 4 3 2 1
D D
Serial Debug J12
Connector
P.32
U53
J5/J6
USB0 A USB Ports
USB0 B
P.30
USB1 C
J3
USB1 D BlueTooth
SCC B P.30
(FIReworks) NC
J24 U58/U59
SERIAL Modem Board Mic/Line In
SCC A Connector Preamps
C P.32 P.27
C
I2C U37/U38
Snapper
Audio Control
Key I2S
P.25
Speaker & Mic
MIC
J19
Line In
J30
Connector Connector
Largo UIDE Ultra ATA/66
Connector
J27
P.26 P.27
U34/U43
P.32
PCI BUS Headphone &
P.16 EIDE0 Speaker Amps
32BITS Optical
EIDE/CSLOT Connector P.26
33MHZ P.32 J26
3.3V J8
J25 Headphone
CardSlot Connector
B CSLOT Connector P.26 B
P.32
VIA
U47
PMU
P.34
SYSTEM BLOCK DIAGRAM
A NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
D 051-6403 E
APPLE COMPUTER INC.
SCALE SHT OF
NONE 3 46
8 7 6 5 4 3 2 1
CR-4
8 7 6 5 4 3 2 1
POWER SYSTEM ARCHITECTURE
D AC D
BACKLIGHT INVERTER
ADAPTER INPUT14_24V
IN
BUCK PBUS
REGULATOR +5V
DCDC_EN MAIN 3V/5V
CHARGER SD
DC/DC CONVERTER
(LTC1625) ON3 (MAX785) +3.3V
ON5
+1.8V LDO +1.41V
L3 I/O
C (LT1962) C
CPU_VCORE
(+1.15V/+1.3V)
DC/DC
(MAX1717)
BACKUP BATTERY CIRCUIT CHARGES OFF PBUS
AND PREVENTS PBUS FROM DROPPING BELOW 6V
(UNTIL DRAINED) SHDN +5V DC/DC +1.25V
(LTC1773) ATI M7_M9 CORE
CHARGER INPUT DCDC_EN
BACKUP SLEEP
BATTERY & BOOST OUTPUT
+5V DC/DC +2.5V ATI M7_M9 DDR CORE AND I/O
B (MAX1644) L3 CORE B
SHDN
DCDC_EN
+3.3V DC/DC +1.8V MAX BUS INTERFACE
(MAX1644) CPU I/O
SHDN
4S 2P LITHIUM ION POWER BLOCK DIAGRAM
A DCDC_EN NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
D 051-6403 E
APPLE COMPUTER INC.
SCALE SHT OF
NONE 4 46
8 7 6 5 4 3 2 1
CR-5
8 7 6 5 4 3 2 1
PCB SPECS BOARD HOLES
D
D CPU HEATSINK MOUNTS TIED TO CHGND1 CARDBUS CONN MOUNTS
ZT3 ZT2 ZT7
140R118 140R118 118R98
1 1 1
THICKNESS : 1.2 MM / 0.047 IN ZT6
140R118
ZT8
235R156
ZT5
118R98
1/2 OZ CU THICKNESS: 0.7 MILS 1 1 1
1.0 OZ CU THICKNESS: 1.4 MILS CHGND1
XH4
22R10
5<> HOLE_22R10A 1
IMPEDANCE : 50 OHMS +/- 10% XH2
DIELECTRIC: FR-4 1
22R10
LAYER COUNT: 10 CHGND7
ZT4
SIGNAL TRACE WIDTH: 4 MILS 1
118R98
PREPREG THICKNESS: 3 - 6 MILS CHGND5
XH1
C 5<> HOLE_22R10D 1
22R10 C
XH3
22R10
1
SEE PCB CAD FILES FOR MORE SPECIFIC INFO.
CHGND6
BOARD STACK-UP AND CONSTRUCTION
PCB BOARD STANDOFFS
Micro Via (Blind) 20R10 TH Via
1 20R10 Buried Via SIGNAL (1/2 OZ) BS1 BS5
140R118 140R118
1 5<> HOLE_22R10A 1
2 SIGNAL (1/2 OZ)
HOLE & SLOT FOR BT CARRIER
BS3
140R118
3 ZT1 5<> HOLE_22R10D 1
GROUND (1/2 OZ) 1
118R98
B SL1
B
4 SIGNAL (1/2 OZ) 1
TH
SL-25X200
5
CUT POWER PLANE(DEFAULT 3V) POWER (1 OZ)
CHGND4B
6 CUT POWER PLANE(DEFAULT 5V) POWER (1 OZ)
7 SIGNAL (1/2 OZ)
8 GROUND (1/2 OZ)
9 SIGNAL (1/2 OZ)
10 SIGNAL (1/2 OZ)
BOARD INFORMATION
A NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
D 051-6403 E
APPLE COMPUTER INC.
SCALE SHT OF
NONE 5 46
8 7 6 5 4 3 2 1
CR-6
8 7 6 5 4 3 2 1
+3V_MAIN +1_8V_MAIN
TABLE_ALT_HEAD
PART NUMBER ALTERNATE FOR
PART NUMBER
BOM OPTION REF DES COMMENTS: R481 +3V_UNIN_MAXPLL_MAIN 43<> 43<> +1_8V_UNIN_MAXPLL_MAIN R440
TABLE_ALT_ITEM
1
22 2 1
22 2
343S1303 343S0347 U9
5% 5%
1/16W 1/16W
MF
402
C662 1 C637 1 1 C638 1 C607 MF
402
4.7uF 0.01uF 0.01uF 4.7uF
N20P80% 20% 20% N20P80%
10V 16V 2 16V 2 10V
CERM 2 CERM 2 CERM CERM MAXBUS PULL-UPS
D
805 402 402 805
+1_8V_SLEEP
D
RP3
2
1K 7
40<> 13> 6<> CPU_TS_L
AE8 AF5 AE6 5%
1/16W
SM1
RP2
MAX_CLKIN_VDD3 MAXPLLAVD MAXPLLDVD 3
10K 6
40<> 6> CPU_TA_L
5%
SYSCLK_UNIN AH2
MAXCLK D_0 AJ28 CPU_DATA<0>
RP2 1/16W
SM1
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