Service Manuals, User Guides, Schematic Diagrams or docs for : asus A3G ASUS_A3G
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5 4 3 2 1
01
FILE LIST
01_BLOCK DIAGRAM
D D
02_POWER DIAGRAM
A3G THERMAL
03_CPU-DOTHAN(HOST)
04_CPU-DOTHAN(PWR)
05_THERMAL
05 06_NB-MCHM1
BLOCK POWER
(IMVP4)
07_NB-MCHM2
08_NB-MCHM3
09_DUAL_DDR
DIAGRAM FAN
DOTHAN
21W
41 42 43 44 45 46 47 48 49 50 51
10_DDR_TERMINATION
11_VGA_M11-Disp Sys
12_VGA_M11-Mem IF
13_VGA_M11-PWR/GND
14_VGA_M11-VM TERMINATION
39 03 04
15_VGA_M11-Video RAM
PSB 16_BACKLIGHT&LCD CON
LVDS 17_TV-OUT & CRT CON
LCD DDR TERMINATION 18_ICH4-M(HUB_PCI)
MCHM 19_ICH4-M(IDE_AC97)
10
C CLOCK TV C/Y/COMP VGA(M11) AGP MONTARA 20_ICH4-M(USB_PM) C
21_ICH4-M(POWER)
GEN -PM 22_CLOCK-ICS950815
RGB 9W DDR
CRT DUAL DDR SODIMM 23_LAN-RTL8100CL
22 11W 24_MINIPCI
11 12 13 14 15 16 17 52 25_CB1394-R5C593(1)
09
06 07 08 26_CB1394-R5C593(2)
27_PCMCIA SOCKET
HUB 28_IDE-HD
Function AC'97 AC97 SECONDARY IDE 29_IDE-ODD
AUDIO AMP IDE 30_KBC-M38857
Key & MIC CODEC 29 31_SuperI/O&FWH
34
Ultra 32_IR&LPT_PORT
40 35 36 ATA100
ICH4 PRIMARY IDE 33_DEBUG PORT
34_CODEC-ALC650
MDC 28 35_AUDIO AMP
2.9W 36_MIC
37
37_MDC&RJ45&RJ11
PCI LPC DEBUG 38_USB
B 39_FAN&Audio DJ B
PORT 40_FUNCTION KEY
18 19 20 21
41_PWR & RESET SEQ
33
42_VCORE
1394 43_VGACORE
CARDBUS MINIPCI LAN USB 2.0 44_SYSTEM
KBC SIO IR&LPT 45_2.5V&1.5V&1.35V&1.05V
46_1.25V&1.8V
25 26 24 23
USB X6 47_PIC16C54C
32
30 31 48_CHARGER
PCMCIA 49_AC_BAT_SYS
38 50_BATLOW/SD#
27 PRINTER 51_LOAD SWITCH
PORT 52_SCREW_HOLES
53_Clock Map
32
54_Platform Power Delivery Map
55_System Power Sequence(1)
56_System Power Sequence(2)
57_Revision History
A A
Title : BLOCK DIAGRAM
ASUSTECH CO.,LTD. Engineer: HD_NB TEAM
Size Project Name Rev
C A3G 2.0
Date: Wednesday, October 13, 2004 Sheet 1 of 53
5 4 3 2 1
5 4 3 2 1
VR_VID0-VR_VID5
D
PM_STPCPU#.,PM_DPRSLPVR.,PCI#.,MCH_OK.,CLK_EN# D
CPU_VRON
+VCORE (25A)
AC_BAT_SYS (2A)
MAX1987
VRM_PWRGD
+VGACORE (8.625A)
(1A)
MAX1844
VGA_PWRGD
SUSC#.
(6A) +5VO (5.5A) SUSB# +V5S (5.5A)
LTC3728 SUSB# +V3.3S (5A)
(2.5A) +12VO (0.2A)
(Regulator) +V5 (5.5A)
+5VAO +V3.3SUS (5A) +V3 (5A)
A/D_VIN SHUT_DOWN#
SUSB# +V12S (0.2A) Power
+V12 (0.2A) BAT_S Signal BAT_IN#_OC
+1.5VO (1.35A) +V1.5 (1.35A)
SUSC# Circuit
C
TS ACIN_OC C
+2.5VO (8.2A) +V2.5 (8.2A) SUSB# +V1.5S (1.35A)
SUSC# AC_APR_UC
(2A) +V2.5S (8.2A)
TPS5130
(4.2A) +1.2VO (1.9A) +V1.2S (1.9A)
SUSB#
+1.05VO (2.8A) +VCCP (2.8A)
SWITCH
CPU_VRON
SUSB#
+V2.5 (0.5A) CM8562 +V1.25S (1A)
(Regulator) TS#
SUSB# PIC16C54B/C CHG EN
SUSC# AC_APR_UC CHG LED
+2.5VO (0.6A) MIC37101-1.8 (0.8A) +1.8VO +V1.8 (0.8A) SMC_BAT PWR LED
LDO SMD_BAT BAT_LLOW
(0.8A) SUSB# +V1.8S (0.8A)
+V3.3SUS (0.7A) SI9183DT +V1.5SUS (1.35A)
B (LDO) B
(2.25A) PIC + TL494 (2.5A) BAT (10.5A)
(Charge)
(10.5A) (10.5A)
FDS6679
+5VO (20mA)
(6.4A) (6.4A) A/D_VIN (10mA) L78L05ACUTR SWITCH
FD6JK3TP +5VLCM (120mA)
(Regulator) +5VCHG (100mA) (F02JK2E)
(2mA) MIC5223MB +3VAO (10mA) +3VALWAYS (10mA) LM4040BIM3X +2.5VREF
(Regulator) (Regulator) (500uA)
A A
Title : POWER DIAGRAM
ASUSTECH CO.,LTD. Engineer: EDDY ZHAO
Size Project Name Rev
C A3G 2.0
Date: Wednesday, October 13, 2004 Sheet 2 of 57
5 4 3 2 1
5 4 3 2 1
CPU Pin A1 need to be enlarged(M) WIDTH: 5 mils
SPACE >= 1:2
U42B H_D#[63:0] <8>
D <8> H_A#[16:3]
H_A#16
GROUP SPACE >=1:5 D
AA2 N2 H_ADS# <7> U42A
H_A#15 A[16]# ADS# Breakout Length:<=200 mil
Y3 A[15]# PRDY# A10 H_PRDY# H_D#15 C25 Y25 H_D#47
H_A#14 D[15]# D[47]#
AA3 A[14]# PREQ# B10 H_PREQ# LENGTH: 1" - 6.5"(OPT: 4"+/-0.5") H_D#14 E23 AA26 H_D#46 WIDTH:4mils
H_A#13 H_D#13 D[14]# D[46]# H_D#45
U1 A[13]# B23 Y23
H_A#12 Y1 L1 H_BNR# <7>
(#0011) H_D#12 C26
D[13]# D[45]#
V26 H_D#44 SPACE >= 1:3
H_A#11 A[12]# BNR# D[12]# D[44]#
Y4 J3 H_BPRI# <7> H_D#11 E24 U25 H_D#43 GROUP SPACE >=1:5
A[11]# BPRI#
ADDRESS GROUP 0
H_A#10 H_D#10 D[11]# D[43]# H_D#42
W2 A[10]# D24 V24
H_A#9 H_D#9 D[10]# D[42]# H_D#41
T4
DATA GROUP 0
2
A[9]# B24 D[9]# D[41]# U26
H_A#8 W1 A7 H_D#8 C20 AA23 H_D#40
A[8]# DBR#
DATA GROUP
H_A#7 D[8]# D[40]#
H_A#6
V2 A[7]#
H_D#7 B20 D[7]# D[39]# R23 H_D#39 LENGTH: 0.5" - 5.5"
R3 H_D#6 A21 R26 H_D#38
H_A#5 V3
A[6]#
H_D#5 B26
D[6]# D[38]#
R24 H_D#37 (#0012)
H_A#4 A[5]# D[5]# D[37]#
U4 L4 H_DEFER# <7> H_D#4 A24 V23 H_D#36
H_A#3 A[4]# DEFER# D[4]# D[36]#
P4 H2 H_DRDY# <7> H_D#3 B21 U23 H_D#35
A[3]# DRDY# D[3]# D[35]#
<8> H_ADSTB#0 U3 M2 H_DBSY# <7> H_D#2 A22 T25 H_D#34
H_REQ#4 ADSTB[0]# DBSY# D[2]# D[34]#
T1 H_D#1 A25 AA24 H_D#33
H_REQ#3 REQ[4]# D[1]# D[33]#
P1 H_D#0 A19 Y26 H_D#32
H_REQ#2 REQ[3]# D[0]# D[32]#
T2 REQ[2]# <8> H_DINV0# D25 T24 H_DINV2# <8>
H_REQ#1 DINV[0]# DINV[2]#
P3 REQ[1]# <8> H_DSTBN#0 C23 W25 H_DSTBN#2 <8>
H_REQ#0 DSTBN[0]# DSTBN[2]#
R2 REQ[0]# <8> H_DSTBP#0 C22 W24 H_DSTBP#2 <8>
H_BR0# DSTBP[0]# DSTBP[2]#
<8> H_REQ#[4:0] N4 H_BR0# <7> +VCCP
CONTROL
BR0#
H_D#31 K25 AF26 H_D#63
R362 H_D#30 D[31]# D[63]# H_D#62
Here IERR# is not routed as N25 D[30]# D[62]# AF22
A4 H_IERR# 1 2 a test point or to any H_D#29 H26 AF25 H_D#61
IERR# D[29]# D[61]#
<8> H_A#[31:17] 0.5"-12" optional system receiver H_D#28 M25 D[28]# D[60]# AD21 H_D#60
H_A#31 AF1 56Ohm H_D#27 N24 AE21 H_D#59
H_A#30 A[31]# D[27]# D[59]#
AE1 A[30]# INIT# B5 <=10" H_INIT# <20,31> H_D#26 L26 D[26]# D[58]# AF20 H_D#58
3
H_A#29 AF3 H_D#25 H_D#57
DATA GROUP 1
A[29]# J25 D[25]# D[57]# AD24
H_A#28 H_D#24 H_D#56
WIDTH:4mils AD6
DATA GROUP
A[28]# M23 AF23
ADDRESS GROUP 1
H_A#27 D[24]# D[56]#
AE2 A[27]# LOCK# J2 <=10" H_LOCK# <7> H_D#23 J23 AE22 H_D#55
SPACE >= 1:2 H_A#26 AD5 H_D#22 G24
D[23]# D[55]#
AD23 H_D#54
H_A#25 A[26]# D[22]# D[54]#
STROBE SPACE >=1:3 AC6 H_D#21 F25 AC25 H_D#53
H_A#24 A[25]# D[21]# D[53]#
AB4 H_D#20 H24 AC22 H_D#52
GROUP SPACE >=1:5 H_A#23 A[24]# D[20]# D[52]#
AD2 H_D#19 M26 AC20 H_D#51
H_A#22 A[23]# D[19]# D[51]#
AE4 RESET# Signal Routing with H_D#18 L23 AB24 H_D#50
H_A#21 A[22]# D[18]# D[50]#
AD3 A[21]# RESET# B11 <=3" H_CPURST# <8> NO ITP700FLEX Connector H_D#17 G25 D[17]# D[49]# AC23 H_D#49
LENGTH: 0.5" - 6.5" H_A#20 AC3 L2 H_RS#2 H_D#16 H23 AB25 H_D#48
H_A#19 A[20]# RS[2]# H_RS#1 D[16]# D[48]#
C AC7 K1 J26 AD20 C
(#0012) H_A#18 AC4
A[19]# RS[1]#
H1 H_RS#0 <8> H_DINV1#
K24
DINV[1]# DINV[3]#
AE24
H_DINV3# <8>
H_A#17 A[18]# RS[0]# <8> H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 <8>
AF4 A[17]# H_RS#[2:0] <7> <8> H_DSTBP#1 L24 AE25 H_DSTBP#3 <8>
DSTBP[1]# DSTBP[3]#
<8> H_ADSTB#1 AE5 ADSTB[1]# TRDY# M3 H_TRDY# <7>
SOCKET479P
HIT# K3 H_HIT# <7>
<6> H_DPWR# 1"-6.5" C19 DPWR# HITM# K4 H_HITM# <7>
SOCKET479P
+VCCP
CPU PLL
1
CIRCUITS H_VID5
R391
H_VID4 VR_VID5 <42> 56Ohm
H_VID3 VR_VID4 <42>
/X
VR_VID3 <42>
2
+V1.8S H_VID2 H_CPURST#
H_VID1 VR_VID2 <42>
H_VID0 VR_VID1 <42>
VR_VID0 <42>
1
1
TOPOLOGY 2A: +VCCP TOPOLOGY 1B: +VCCP
C426 C425
Open Drain (OD) Signal Open Drain (OD) Signal
2
2
0.01uF/25V 10uF R-CPU-ICH Y-FORK CPU-ICH-R
1
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