Service Manuals, User Guides, Schematic Diagrams or docs for : asus F70SL
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5 4 3 2 1
F70SL Main BD. R1.0 BLOCK DIAGRAM
CPU Thermal
D
Merom2-3 5
D
LVDS FSB
LCD Clock GEN
533/667/800 4
17
RGB PCIE 0-15 North DDR2 SO-DIMM X2
CRT NV NB9M-GS Bridge DDR2
53 12-14
18 533/667 Mhz
Sis 671DX
TMDS 6-11
HDMI
16 MuTIOL 1G
C C
LPC South 2nd HDD
Debug CON Bridge IDE 88SA8052 SATA
44 32 32
Sis 968 SATA
EC 20-24
1ST HDD
ITE8512 USB 32
30-31
ODD
32
PCIE
AZALIA New CCD
B
SPI ROM LED Card 17 B
30 56
29
KB/TOUCH PAD Blue Tooth
38
31,70
Audio Mini Card
WLAN USB2.0 *4
Amp Codec 19
62
26
ALC663 10/100/1000M
25
4 in 1 Card
Giga RTL8211B Reader
33,36 42
A A
JACK(SPIDIF)/MIC
27
Title : Block Diagram
ASUSTeK Computer INC Engineer: Miller / Daniel
Size Project Name Rev
B F70SL 1.0
Date: Monday, November 03, 2008 Sheet 1 of 94
5 4 3 2 1
5 4 3 2 1
6 H_A#[16..3]
6 H_REQ#[4..0]
6 H_A#[35..17]
T203
H_D#[0..63] 6
1
U201A
H_A#3 J4 H1 H_ADS#
A[3]# ADS# H_ADS# 6
ADDR GROUP 0
ADDR GROUP 0
H_A#4 L5 E2 H_BNR# U201B
A[4]# BNR# H_BNR# 6
H_A#5 L4 G5 H_BPRI# H_D#0 E22 Y22 H_D#32
A[5]# BPRI# H_BPRI# 6 D[0]# D[32]#
H_A#6 K5 H_D#1 F24 AB24 H_D#33
H_A#7 A[6]# H_DEFER# H_D#2 D[1]# D[33]# H_D#34
M3 H5 H_DEFER# 6 E26 V24
D
H_A#8 A[7]# DEFER# H_DRDY# H_D#3 D[2]# D[34]# H_D#35 D
N2 F21 H_DRDY# 6 G22 V26
A[8]# DRDY# D[3]# D[35]#
DATA GRP 0
DATA GRP 0
H_A#9 J1 E1 H_DBSY# H_D#4 F23 V23 H_D#36
A[9]# DBSY# H_DBSY# 6 D[4]# D[36]#
H_A#10 N3 H_D#5 G25 T22 H_D#37
H_A#11 A[10]# H_BR0# R203 H_D#6 D[5]# D[37]# H_D#38
P5 F1 H_BR0# 6 E25 U25
H_A#12 A[11]# BR0# 56Ohm H_D#7 D[6]# D[38]# H_D#39
P2 E23 U23
A[12]# D[7]# D[39]#
CONTROL
H_A#13 L2 D20 H_IERR# H_D#8 K24 Y25 H_D#40
A[13]# IERR# +VCCP_AGTL+ D[8]# D[40]#
DATA GRP 2
H_A#14 P4 B3 H_INIT# H_D#9 G24 W22 H_D#41
A[14]# INIT# H_INIT# 24 D[9]# D[41]#
H_A#15 P1 H_D#10 J24 Y23 H_D#42
H_A#16 A[15]# H_LOCK# H_D#11 D[10]# D[42]# H_D#43
R1 H4 H_LOCK# 6 J23 W24
H_ADSTB#0 A[16]# LOCK# H_D#12 D[11]# D[43]# H_D#44
6 H_ADSTB#0 M1 2 1 +VCCP_AGTL+ H22 W25
ADSTB[0]# H_CPURST# H_D#13 D[12]# D[44]# H_D#45
C1 H_CPURST# 6 F26 AA23
RESET# D[13]# D[45]#
1
H_REQ#0 K3 F3 H_RS#0 R201 H_D#14 K22 AA24 H_D#46
REQ[0]# RS[0]# H_RS#0 6 D[14]# D[46]#
H_REQ#1 H2 F4 H_RS#1 51Ohm @ H_D#15 H23 AB25 H_D#47
REQ[1]# RS[1]# H_RS#1 6 D[15]# D[47]#
H_REQ#2 K2 G3 H_RS#2 H_DSTBN#0 J26 Y26 H_DSTBN#2
REQ[2]# RS[2]# H_RS#2 6 T201 6 H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 6
H_REQ#3 J3 G2 H_TRDY# H_DSTBP#0 H26 AA26 H_DSTBP#2
REQ[3]# TRDY# H_TRDY# 6 6 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 6
H_REQ#4 L1 H_DINV#0 H25 U22 H_DINV#2
REQ[4]# 6 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 6
G6 H_HIT# H_CPURST#
HIT# H_HIT# 6
1
H_A#17 Y2 E4 H_HITM#
A[17]# HITM# H_HITM# 6
H_A#18 U5 R230 H_D#16 N22 AE24 H_D#48
A[18]# D[16]# D[48]#
H_A#19 R3 AD4 HBPM0# 1 4.7KOhm H_D#17 K25 AD24 H_D#49 Layout Note:
A[19]# BPM[0]# D[17]# D[49]#
ADDR GROUP 1
ADDR GROUP 1
H_A#20 W6 AD3 HBPM1# T214 @ H_D#18 P26 AA21 H_D#50 Comp0,2 connect with Z0=27.4 ohm,
H_A#21 A[20]# BPM[1]# HBPM2# H_D#19 D[18]# D[50]# H_D#51
U4 AD1 1 R23 AB22 make trace length shorter than 0.5".
2
A[21]# BPM[2]# D[19]# D[51]#
XDP/ITP SIGNALS
H_A#22 Y5 AC4 HBPM3# 1 T217 H_D#20 L23 AB21 H_D#52
A[22]# BPM[3]# D[20]# D[52]# Comp1,3 connect with Z0=54.9 ohm,
DATA GRP 1
DATA GRP 1
H_A#23 U1 AC2 HBPM4# 1 T218 H_D#21 M24 AC26 H_D#53
H_A#24 A[23]# PRDY# HBPM5# T219 H_D#22 D[21]# D[53]# H_D#54 make trace length shorter than 0.5".
R4 AC1 L22 AD20
H_A#25 A[24]# PREQ# H_TCK H_D#23 D[22]# D[54]# H_D#55 Comp[3:0] at least 25 mils away from
H_A#26
T5
T3
A[25]# TCK
AC5
AA6 H_TDI CPU GND
H_D#24
M23
P25
D[23]# D[55]#
AE22
AF23 H_D#56 any other toggling signal.
A[26]# TDI D[24]# D[56]#
H_A#27
H_A#28
W2
A[27]# TDO
AB3 H_TDO
H_TMS
Debug H_D#25
H_D#26
P23
D[25]# D[57]#
AC25 H_D#57
H_D#58
27.4 ohm connects with an ~18mil
W5 AB5 P22 AE21 wide trace to comp0.
A[28]# TMS D[26]# D[58]#
DATA GRP 3
H_A#29 Y4
A[29]# TRST#
AB6 H_TRST# Port +VCCP_AGTL+
H_D#27 T24
D[27]# D[59]#
AD21 H_D#59
54.9 ohm connect with 5mil-wide
H_A#30 U2 C20 CPU_DBR# 1 T202 H_D#28 R24 AC22 H_D#60
H_A#31 A[30]# DBR# TPC28T H_D#29 D[28]# D[60]# H_D#61 to comp1
V4 L25 AD23
H_A#32 A[31]# H_D#30 D[29]# D[61]# H_D#62
W3 @ T25 AF22
A[32]# D[30]# D[62]#
2
H_A#33 AA4 THERMAL <500 mil (55 Ohm) H_D#31 N25 AC23 H_D#63
H_A#34 A[33]# R215 H_DSTBN#1 D[31]# D[63]# H_DSTBN#3
AB2 T/B trace 5.5 6 H_DSTBN#1 L26 AE25 H_DSTBN#3 6
H_A#35 A[34]# H_PROCHOT_S# 1KOhm H_DSTBP#1 DSTBN[1]# DSTBN[3]# H_DSTBP#3
AA3 D21 6 H_DSTBP#1 M26 AF24 H_DSTBP#3 6
H_ADSTB#1 A[35]# PROCHOT# CPU_THRM_DA Space 25 1% H_DINV#1 DSTBP[1]# DSTBP[3]# H_DINV#3
6 H_ADSTB#1 V1 A24 CPU_THRM_DA 5 6 H_DINV#1 N24 AC20 H_DINV#3 6
ADSTB[1]# THRMDA CPU_THRM_DC DINV[1]# DINV[3]#
C B25 CPU_THRM_DC 5
C
1
H_A20M# THRMDC GTL_REF H_COMP0 R213 27.4Ohm 1%
24 H_A20M# A6 AD26 R26 1 2
A20M# GTLREF COMP[0]
ICH
ICH
21,24 H_FERR#
H_FERR# A5
FERR# THERMTRIP#
C7 PM_THRMTRIP#
PM_THRMTRIP# 21,24
R220 2 1 1KOhm @ C23
TEST1
MISC COMP[1]
U26 H_COMP1 R207 1 2 54.9Ohm 1% GND
2
H_IGNNE# C4 C5507 R221 2 1 51.1Ohm @ D25 AA1 H_COMP2 R216 1 2 27.4Ohm 1%
21,24 H_IGNNE# IGNNE# TEST2 COMP[2]
1
1
C201 R205 T211 1 C24 Y1 H_COMP3 R206 1 2 54.9Ohm 1%
H_STPCLK# 0.1UF/10V 2KOhm C203 TEST3 COMP[3]
21,24 H_STPCLK# D5 1 2 0.1UF/10V @ AF26
H_INTR STPCLK# TEST4 H_DPRSTP#
21,24 H_INTR C6 H CLK 10UF/10V 1% T212 1 AF1 E5 H_DPRSTP# 21,24,80
2
2
H_NMI LINT0 CLK_CPU_BCLK T213 TEST5 DPRSTP# H_DPSLP#
21,24 H_NMI B4 A22 CLK_CPU_BCLK 4 1 A26 B5 H_DPSLP# 24
1
H_SMI# LINT1 BCLK[0] CLK_CPU_BCLK# TEST6 DPSLP# H_DPWR#
21,24 H_SMI# A3 A21 CLK_CPU_BCLK# 4 D24 H_DPWR# 6
SMI# BCLK[1] DPWR#
2
GND CPU_BSEL0 B22 D6 H_PWRGD
4 CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGD 6
M4 GND GND CPU_BSEL1 B23 D7 1 R219
RSVD1 4,7 CPU_BSEL1 BSEL[1] SLP#
N5 CLK_CPU_BCLK 1 CPU_BSEL2 C21 AE6 T204 10OHM
RSVD2 4 CPU_BSEL2 BSEL[2] PSI#
T2 T205 H_CPUSLP#
RSVD3 H_CPUSLP# 21,24
V3 SOCKET478B PM_PSI# @
PM_PSI# 80
1
RSVD4
BCLK FSB BSEL2 BSEL1 BSEL0
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