Service Manuals, User Guides, Schematic Diagrams or docs for : asus K40IN BLOCK DIAGRAM
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5 4 3 2 1
K40IN
BLOCK DIAGRAM CPU
MERON;PENRYN
XDP Discharge Circuit
Page 67 Page 57
Page 3~5
D D
zHM6601;zHM008 BSF Thermal Sensor
Maxim MAX6657 Switch & LED
2RDD
2 DDRII So-DIMMx2 Page 50 Page 41
LCD Panel 800
Page 45 Page 6,8~9
PWM Fan DC Conn.
Page 50 Page 60
CRT
Page 46
Onboard DRAM Skew Holes Battery Conn.
Page 65 Page 60
Page 9~10
ODD
Page 51
MCP75
HDD
C
Page 54 Power C
VCORE
1x EICP MiniCard Page 80
WWAN
Page 53 System
Page 81
GigaLAN 1.05VSUS
REALTEK 8112 Transformer Page 82
Page 33~34
DDR & VTT
CPL Page 83
Debug Conn.
Page 44 +1.5VS
B B
Touchpad Page 84
Page 31
EC
8502
Charger
Keyboard Page 88
Page 30
Page 31
BSU
BSU
BSU
BSU MiniCard
SPI ROM WWAN
Detect
Page 90
Page 30 Page 53
USB Port
Page 52 Load Switch
CMOS Camera Page 91
USB Port Page 45
Audio Amp ailazA Page 52 Power Protect
Page 39
Azalia Codec Page 92
Realtek ALC269 USB Port
Jack Page 52
A Page 36 A
Page 37
USB Port
Page 52
CardReader Title :Block Diagram
Page 17~26 ASUSTeK COMPUTER INC. NB6 Engineer: Tony Kao
Page 54
Size Project Name Rev
Custom G71G 1.0
Date: Friday, February 13, 2009 Sheet 1 of 91
5 4 3 2 1
A B C D E
1
Reset 1
IC
PWR_SW# 6 Power On
2 SWITCH
+5VA 1 8
AC_BAT_SYS 5 PM_RSMRST#
+3VA +3VA_EC SLP_S5#
EC PWRGD_SB
+3VA_EC
7 PM_PWRBTN# To EC
IT8752 10
3 PWRBTN#
VSUS_ON SLP_S3#
CPU_PWRGD
+1.05VSUS
SUSC_EC#
SUSB_EC#
+3VSUS 4 SUS_PWRGD 15
MCP79
+5VSUS PM_PWROK
H_PWRGD
2 2
+12VSUS PS_PWRGD
20
PCI_RESET#
9 11
ALL_SYSTEM_PWRGD
STR_EN# 21
+0.9V 14 VRM_PWRGD
+1.8V
+3V 13 CPU_VRON
SUSC#_PWR
+5V 22
CPU_VLD
+12V
9 H_CPURST#
CPU_RESET# Penryn
SUSC_EC# 12
1Kohm CPUVDD_EN
LPC_RESET#
MCP_VDD_CORE
3
+1.05VS 19 18 3
+1.5VS
CPU_PWRGD
CPU_VRON
ROMSTRAP To ROM
+1.8VS
Unused!!
+2.5VS
+3VS
SUSB#_PWR +5VS
+12VS
17 16
11 Power On Sequence
SUSB_EC#
1Kohm
1 22
+VCORE
4 4
5 5
Title : Schematic Information
ASUSTeK COMPUTER INC. NB6 Engineer: Keirui Shen
Size Project Name Rev
A2 G71G 1.0
Date: Friday, February 13, 2009 Sheet 2 of 91
A B C D E
5 4 3 2 1
H_D#[63:0]
[17] H_D#[63:0]
H_A#[35:3] +VCCP_CPU +VCCP_CPU
[17] H_A#[35:3] QC
H_REQ#[4:0]
[17] H_REQ#[4:0]
2
2
R0342 R343
51Ohm 51Ohm
Place beside CPU ball out
1
1
T0318 BPM_2[0]# BPM_2[1]#
T0319
D D
1
+VCCP_CPU
U8802A U8802B
1
H_A#3 J4 H1 H_D#0 E22 Y22 H_D#32
A[3]# ADS# H_ADS# [17] D[0]# D[32]#
2
ADDR GROUP 0
H_A#4 L5 E2 H_D#1 F24 AB24 H_D#33
A[4]# BNR# H_BNR# [17] D[1]# D[33]#
H_A#5 L4 G5 H_D#2 E26 V24 H_D#34 R344
A[5]# BPRI# H_BPRI# [17] D[2]# D[34]#
H_A#6 K5 H_D#3 G22 V26 H_D#35 51Ohm
A[6]# D[3]# D[35]#
DATA GRP 0
H_A#7 M3 H5 H_D#4 F23 V23 H_D#36
A[7]# DEFER# H_DEFER# [17] D[4]# D[36]#
H_A#8 N2 F21 H_D#5 G25 T22 H_D#37
H_DRDY# [17]
1
H_A#9 A[8]# DRDY# H_D#6 D[5]# D[37]# H_D#38 BPM_2[2]#
J1 A[9]# DBSY# E1 H_DBSY# [17] E25 D[6]# D[38]# U25
H_A#10 H_D#7 H_D#39
H_A#11
N3
P5
A[10]#
A[11]# BR0# F1 H_BR0# [17]
QC H_D#8
E23
K24
D[7]#
D[8]#
D[39]#
D[40]#
U23
Y25 H_D#40
DATA GRP 2
H_A#12 P2 H_D#9 G24 W22 H_D#41
A[12]# T317 D[9]# D[41]#
CONTROL
H_A#13 L2 D20 H_IERR# 1 H_D#10 J24 Y23 H_D#42
H_A#14 A[13]# IERR# H_D#11 D[10]# D[42]# H_D#43
P4 A[14]# INIT# B3 H_INIT# [17] J23 D[11]# D[43]# W24
H_A#15 P1 H_D#12 H22 W25 H_D#44
H_A#16 A[15]# 100Ohm 1% H_D#13 D[12]# D[44]# H_D#45
R1 A[16]# LOCK# H4 H_LOCK# [17] F26 D[13]# D[45]# AA23
M1 1 2 H_D#14 K22 AA24 H_D#46
[17] H_ADSTB#0 ADSTB[0]# H_CPURST#_XDP [67] D[14]# D[46]#
C1 H_D#15 H23 AB25 H_D#47
RESET# H_CPURST# [17] D[15]# D[47]#
H_REQ#0 K3 F3 R0337 J26 Y26
REQ[0]# RS[0]# H_RS#0 [17] [17] H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 [17]
H_REQ#1 H2 F4 H26 AA26
REQ[1]# RS[1]# H_RS#1 [17] [17] H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 [17]
H_REQ#2 K2 G3 H25 U22
REQ[2]# RS[2]# H_RS#2 [17] [17] H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 [17]
H_REQ#3 J3 G2
REQ[3]# TRDY# H_TRDY# [17]
H_REQ#4 L1 REQ[4]# H_D#16 H_D#48
HIT# G6 H_HIT# [17] N22 D[16]# D[48]# AE24
H_A#17 Y2 E4 H_D#17 K25 AD24 H_D#49
A[17]# HITM# H_HITM# [17] D[17]# D[49]#
H_A#18 U5 H_D#18 P26 AA21 H_D#50
H_A#19 A[18]# H_D#19 D[18]# D[50]# H_D#51
R3 A[19]# BPM[0]# AD4 XDP_BPM#0 [67] R23 D[19]# D[51]# AB22
ADDR GROUP 1
H_A#20 W6 AD3 H_D#20 L23 AB21 H_D#52
A[20]# BPM[1]# XDP_BPM#1 [67] D[20]# D[52]#
DATA GRP 1
C H_A#21 U4 AD1 H_D#21 M24 AC26 H_D#53 C
A[21]# BPM[2]# XDP_BPM#2 [67] D[21]# D[53]#
XDP/ITP SIGNALS
H_A#22 Y5 AC4 H_D#22 L22 AD20 H_D#54
H_A#23
H_A#24
H_A#25
H_A#26
U1
R4
T5
A[22]#
A[23]#
A[24]#
A[25]#
BPM[3]#
PRDY#
PREQ#
TCK
AC2
AC1
AC5
XDP_BPM#3 [67]
XDP_BPM#4
XDP_BPM#5
XDP_TCK
[67]
[67]
[67]
H_D#23
H_D#24
H_D#25
H_D#26
M23
P25
P23
D[22]#
D[23]#
D[24]#
D[25]#
D[54]#
D[55]#
D[56]#
D[57]#
AE22
AF23
AC25
H_D#55
H_D#56
H_D#57
H_D#58
QC Comp 0,2: Zo=25 Ohm, trace length < 0.5"
T3 AA6 XDP_TDI [67] P22 AE21
A[26]# TDI D[26]# D[58]# Comp 1,3: Z0=50 Ohm, trace length < 0.5"
DATA GRP 3
H_A#27 W2 AB3 +VCCP_CPU H_D#27 T24 AD21 H_D#59
H_A#28 A[27]# TDO XDP_TDO [67] H_D#28 D[27]# D[59]# H_D#60
W5 AB5 R24 AC22
H_A#29 Y4
A[28]#
A[29]#
TMS
TRST# AB6
XDP_TMS
XDP_TRST#
[67]
[67]
H_D#29 L25
D[28]#
D[29]#
D[60]#
D[61]# AD23 H_D#61
DC
2
H_A#30 U2 C20 H_D#30 T25 AF22 H_D#62
H_A#31 A[30]# DBR# XDP_DBR# [67] R0315 H_D#31 D[30]# D[62]# H_D#63
H_A#32
V4 A[31]# N25 D[31]# D[63]# AC23 Comp 0,2: Zo=27.4 Ohm, trace length < 0.5"
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